set_property CLOCK_DEDICATED_ROUTE BACKBONE

joe

实验条件：
zynq xc7z035ffg676-2
PL DDR3
vivado 2018.3

block design图：

generate output 出现如下提示：
[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
        < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_1] >

        design_1_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y274
         design_1_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y6

        The above error could possibly be related to other connected instances. Following is a list of
        all the related clock rules and their respective instances.

        Clock Rule: rule_mmcm_bufg
        Status: PASS
        Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
         design_1_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y6
         and design_1_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

解决：
如果时钟输入引脚需要驱动不同时钟域的CMT（MMCM/PLL）模块，那么约束CLOCK_DEDICATED_ROUTE=BACKBONE是必须的。
是什么情况会导致时钟输入与CMT不在一个时钟域呢？当一组外部接口时序，其时钟信号输入FPGA的一个I/O Bank，而相应的数据信号则在另一个I/O Bank输入，并且此时需对时钟信号进行分频，分频后的时钟用作输入数据的采集。

joe

还可以参考：http://xilinx.eetrend.com/blog/2021/100554402.html