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楼主 |
发表于 2021-8-17 21:08:55
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对应产生的verilog代码如下:
module Alu(
input clock,
input reset,
input [31:0] io_a,
input [31:0] io_b,
input [1:0] io_k,
output [31:0] io_f
);
wire _T = io_k == 2'h0; // @[Alu.scala 24:13]
wire [31:0] _T_2 = io_a + io_b; // @[Alu.scala 25:18]
wire _T_3 = io_k == 2'h1; // @[Alu.scala 26:20]
wire [31:0] _T_5 = io_a - io_b; // @[Alu.scala 27:18]
wire _T_6 = io_k == 2'h2; // @[Alu.scala 28:20]
wire [31:0] _T_7 = io_a | io_b; // @[Alu.scala 29:18]
wire [31:0] _T_8 = io_a & io_b; // @[Alu.scala 31:18]
wire [31:0] _GEN_0 = _T_6 ? _T_7 : _T_8; // @[Alu.scala 28:29]
wire [31:0] _GEN_1 = _T_3 ? _T_5 : _GEN_0; // @[Alu.scala 26:28]
assign io_f = _T ? _T_2 : _GEN_1; // @[Alu.scala 14:8 Alu.scala 25:10 Alu.scala 27:10 Alu.scala 29:10 Alu.scala 31:10]
endmodule
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