chisel中使用scala的循环与不使用循环的对比

joe · 发表于 2021-9-30 09:54:02

在基于chisel/verilog的mini路由器实现之源码这个帖子中用这么一段代码：
when(io.outs(idx).ready) { //输出接口（MASTER）收到下游发来的已准备好接收数据ready信号
  io.in.deq() //发出ready指示输入接口收到的数据OK, 也就是说此时pkt中收到的io.in.bits是真正的有效的数据了
  io.outs(idx).enq(pkt) //输出接口调用enq(pkt)表示发出数据有效valid指示并将数据（其实是通过组合逻辑得到的输入接口中的封包数据）也输出
  printf("got packet to route header %d, data %d, being routed to out(%d)\n",pkt.header,pkt.body,tbl(pkt.header))
}

如果换成：
for(i <- 0 until n) {
  when(io.outs(i).ready && (idx === i.U)) {
io.in.deq() //发出ready指示输入接口收到的数据OK, 也就是说此时pkt中收到的io.in.bits是真正的有效的数据了
io.outs(idx).enq(pkt) //输出接口调用enq(pkt)表示发出数据有效valid指示并将数据（其实是通过组合逻辑得到的输入接口中的封包数据）也输出
printf("got packet to route header %d, data %d, being routed to out(%d)\n",pkt.header,pkt.body,tbl(pkt.header))
  }
}

其实这两段代码的意思差不多，都是在4个输出接口中选择一个用来输出数据，后面一段代码用了scala的for循环。
我没有仔细看两者产生的verilog有什么不同，我相信应该最终要实现的效果是一样的，但只比较两者产生的verilog代码长度，
却发现后面一段的代码产生的verilog比较长。所以如果没有必要，还是尽量少用scala的循环语句,耗费资源。

joe · 发表于 2021-9-30 09:54:57

第一段代码产生的verilog如下，共189行:
module Router(
  input       clock,
  input       reset,
  output       io_read_routing_table_request_ready,
  input       io_read_routing_table_request_valid,
  input  [31:0] io_read_routing_table_request_bits_addr,
  input       io_read_routing_table_response_ready,
  output       io_read_routing_table_response_valid,
  output [31:0] io_read_routing_table_response_bits,
  output       io_load_routing_table_request_ready,
  input       io_load_routing_table_request_valid,
  input  [31:0] io_load_routing_table_request_bits_addr,
  input  [63:0] io_load_routing_table_request_bits_data,
  output       io_in_ready,
  input       io_in_valid,
  input  [7:0]  io_in_bits_header,
  input  [63:0] io_in_bits_body,
  input       io_outs_0_ready,
  output       io_outs_0_valid,
  output [7:0]  io_outs_0_bits_header,
  output [63:0] io_outs_0_bits_body,
  input       io_outs_1_ready,
  output       io_outs_1_valid,
  output [7:0]  io_outs_1_bits_header,
  output [63:0] io_outs_1_bits_body,
  input       io_outs_2_ready,
  output       io_outs_2_valid,
  output [7:0]  io_outs_2_bits_header,
  output [63:0] io_outs_2_bits_body,
  input       io_outs_3_ready,
  output       io_outs_3_valid,
  output [7:0]  io_outs_3_bits_header,
  output [63:0] io_outs_3_bits_body
);
  reg [2:0] tbl [0:14]; // @[Router.scala 55:16]
  reg [31:0] _RAND_0;
  wire [2:0] tbl__T_6_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_6_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_1;
  wire [2:0] tbl__T_13_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_13_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_2;
  wire [2:0] tbl__T_17_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_17_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_3;
  wire [2:0] tbl__T_8_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_8_addr; // @[Router.scala 55:16]
  wire  tbl__T_8_mask; // @[Router.scala 55:16]
  wire  tbl__T_8_en; // @[Router.scala 55:16]
  wire  _T_4 = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Router.scala 86:44]
  wire  _T_10 = ~reset; // @[Router.scala 96:11]
  wire  _GEN_4 = 2'h1 == tbl__T_13_data[1:0] ? io_outs_1_ready : io_outs_0_ready; // @[Router.scala 102:30]
  wire  _GEN_8 = 2'h2 == tbl__T_13_data[1:0] ? io_outs_2_ready : _GEN_4; // @[Router.scala 102:30]
  wire  _GEN_12 = 2'h3 == tbl__T_13_data[1:0] ? io_outs_3_ready : _GEN_8; // @[Router.scala 102:30]
  wire  _GEN_16 = 2'h0 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_17 = 2'h1 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_18 = 2'h2 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_19 = 2'h3 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_29 = _GEN_12 & _GEN_16; // @[Router.scala 102:30]
  wire  _GEN_30 = _GEN_12 & _GEN_17; // @[Router.scala 102:30]
  wire  _GEN_31 = _GEN_12 & _GEN_18; // @[Router.scala 102:30]
  wire  _GEN_32 = _GEN_12 & _GEN_19; // @[Router.scala 102:30]
  wire  _GEN_46 = io_in_valid & _GEN_12; // @[Router.scala 97:27]
  wire  _GEN_47 = io_in_valid & _GEN_29; // @[Router.scala 97:27]
  wire  _GEN_48 = io_in_valid & _GEN_30; // @[Router.scala 97:27]
  wire  _GEN_49 = io_in_valid & _GEN_31; // @[Router.scala 97:27]
  wire  _GEN_50 = io_in_valid & _GEN_32; // @[Router.scala 97:27]
  wire  _GEN_68 = io_load_routing_table_request_valid ? 1'h0 : io_in_valid; // @[Router.scala 91:51]
  wire  _GEN_69 = io_load_routing_table_request_valid ? 1'h0 : _GEN_46; // @[Router.scala 91:51]
  wire  _GEN_70 = io_load_routing_table_request_valid ? 1'h0 : _GEN_47; // @[Router.scala 91:51]
  wire  _GEN_71 = io_load_routing_table_request_valid ? 1'h0 : _GEN_48; // @[Router.scala 91:51]
  wire  _GEN_72 = io_load_routing_table_request_valid ? 1'h0 : _GEN_49; // @[Router.scala 91:51]
  wire  _GEN_73 = io_load_routing_table_request_valid ? 1'h0 : _GEN_50; // @[Router.scala 91:51]
  wire [2:0] _GEN_87 = _T_4 ? tbl__T_6_data : 3'h0; // @[Router.scala 86:84]
  wire  _GEN_112 = ~_T_4; // @[Router.scala 96:11]
  wire  _GEN_113 = _GEN_112 & io_load_routing_table_request_valid; // @[Router.scala 96:11]
  wire  _GEN_115 = ~io_load_routing_table_request_valid; // @[Router.scala 105:13]
  wire  _GEN_116 = _GEN_112 & _GEN_115; // @[Router.scala 105:13]
  wire  _GEN_117 = _GEN_116 & io_in_valid; // @[Router.scala 105:13]
  wire  _GEN_118 = _GEN_117 & _GEN_12; // @[Router.scala 105:13]
  assign tbl__T_6_addr = io_read_routing_table_request_bits_addr[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_6_data = tbl[tbl__T_6_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_6_data = tbl__T_6_addr >= 4'hf ? _RAND_1[2:0] : tbl[tbl__T_6_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_13_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_13_data = tbl[tbl__T_13_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_13_data = tbl__T_13_addr >= 4'hf ? _RAND_2[2:0] : tbl[tbl__T_13_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_17_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_17_data = tbl[tbl__T_17_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_17_data = tbl__T_17_addr >= 4'hf ? _RAND_3[2:0] : tbl[tbl__T_17_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_8_data = io_load_routing_table_request_bits_data[2:0];
  assign tbl__T_8_addr = io_load_routing_table_request_bits_addr[3:0];
  assign tbl__T_8_mask = 1'h1;
  assign tbl__T_8_en = _T_4 ? 1'h0 : io_load_routing_table_request_valid;
  assign io_read_routing_table_request_ready = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Decoupled.scala 72:20 Decoupled.scala 65:20]
  assign io_read_routing_table_response_valid = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_read_routing_table_response_bits = {{29'd0}, _GEN_87}; // @[Router.scala 63:39 Decoupled.scala 48:19]
  assign io_load_routing_table_request_ready = _T_4 ? 1'h0 : io_load_routing_table_request_valid; // @[Decoupled.scala 72:20 Decoupled.scala 65:20]
  assign io_in_ready = _T_4 ? 1'h0 : _GEN_69; // @[Decoupled.scala 72:20 Decoupled.scala 65:20]
  assign io_outs_0_valid = _T_4 ? 1'h0 : _GEN_70; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_outs_0_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_0_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_1_valid = _T_4 ? 1'h0 : _GEN_71; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_outs_1_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_1_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_2_valid = _T_4 ? 1'h0 : _GEN_72; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_outs_2_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_2_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_3_valid = _T_4 ? 1'h0 : _GEN_73; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_outs_3_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19]
  assign io_outs_3_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
  `ifdef RANDOMIZE
`ifdef INIT_RANDOM
   `INIT_RANDOM
`endif
`ifndef VERILATOR
   `ifdef RANDOMIZE_DELAY
      #`RANDOMIZE_DELAY begin end
   `else
      #0.002 begin end
   `endif
`endif
  _RAND_0 = {1{`RANDOM}};
  `ifdef RANDOMIZE_MEM_INIT
  for (initvar = 0; initvar < 15; initvar = initvar+1)
tbl[initvar] = _RAND_0[2:0];
  `endif // RANDOMIZE_MEM_INIT
  _RAND_1 = {1{`RANDOM}};
  _RAND_2 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
  `endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
  always @(posedge clock) begin
if(tbl__T_8_en & tbl__T_8_mask) begin
   tbl[tbl__T_8_addr] <= tbl__T_8_data; // @[Router.scala 55:16]
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_113 & _T_10) begin
      $fwrite(32'h80000002,"setting tbl(%d) to %d\n",io_load_routing_table_request_bits_addr,io_load_routing_table_request_bits_data); // @[Router.scala 96:11]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_118 & _T_10) begin
      $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,io_in_bits_body,tbl__T_17_data); // @[Router.scala 105:13]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
  end
endmodule

joe · 发表于 2021-9-30 09:55:41

第二段代码产生的verilog，共295行：
module Router(
  input       clock,
  input       reset,
  output       io_read_routing_table_request_ready,
  input       io_read_routing_table_request_valid,
  input  [31:0] io_read_routing_table_request_bits_addr,
  input       io_read_routing_table_response_ready,
  output       io_read_routing_table_response_valid,
  output [31:0] io_read_routing_table_response_bits,
  output       io_load_routing_table_request_ready,
  input       io_load_routing_table_request_valid,
  input  [31:0] io_load_routing_table_request_bits_addr,
  input  [63:0] io_load_routing_table_request_bits_data,
  output       io_in_ready,
  input       io_in_valid,
  input  [7:0]  io_in_bits_header,
  input  [63:0] io_in_bits_body,
  input       io_outs_0_ready,
  output       io_outs_0_valid,
  output [7:0]  io_outs_0_bits_header,
  output [63:0] io_outs_0_bits_body,
  input       io_outs_1_ready,
  output       io_outs_1_valid,
  output [7:0]  io_outs_1_bits_header,
  output [63:0] io_outs_1_bits_body,
  input       io_outs_2_ready,
  output       io_outs_2_valid,
  output [7:0]  io_outs_2_bits_header,
  output [63:0] io_outs_2_bits_body,
  input       io_outs_3_ready,
  output       io_outs_3_valid,
  output [7:0]  io_outs_3_bits_header,
  output [63:0] io_outs_3_bits_body
);
  reg [2:0] tbl [0:14]; // @[Router.scala 55:16]
  reg [31:0] _RAND_0;
  wire [2:0] tbl__T_6_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_6_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_1;
  wire [2:0] tbl__T_13_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_13_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_2;
  wire [2:0] tbl__T_18_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_18_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_3;
  wire [2:0] tbl__T_25_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_25_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_4;
  wire [2:0] tbl__T_32_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_32_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_5;
  wire [2:0] tbl__T_39_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_39_addr; // @[Router.scala 55:16]
  reg [31:0] _RAND_6;
  wire [2:0] tbl__T_8_data; // @[Router.scala 55:16]
  wire [3:0] tbl__T_8_addr; // @[Router.scala 55:16]
  wire  tbl__T_8_mask; // @[Router.scala 55:16]
  wire  tbl__T_8_en; // @[Router.scala 55:16]
  wire  _T_4 = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Router.scala 86:44]
  wire  _T_10 = ~reset; // @[Router.scala 96:11]
  wire  _T_14 = tbl__T_13_data == 3'h0; // @[Router.scala 103:37]
  wire  _T_15 = io_outs_0_ready & _T_14; // @[Router.scala 103:29]
  wire  _GEN_0 = 2'h0 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_1 = 2'h1 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_2 = 2'h2 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_3 = 2'h3 == tbl__T_13_data[1:0]; // @[Decoupled.scala 47:20]
  wire  _GEN_13 = _T_15 & _GEN_0; // @[Router.scala 103:47]
  wire  _GEN_14 = _T_15 & _GEN_1; // @[Router.scala 103:47]
  wire  _GEN_15 = _T_15 & _GEN_2; // @[Router.scala 103:47]
  wire  _GEN_16 = _T_15 & _GEN_3; // @[Router.scala 103:47]
  wire  _T_21 = tbl__T_13_data == 3'h1; // @[Router.scala 103:37]
  wire  _T_22 = io_outs_1_ready & _T_21; // @[Router.scala 103:29]
  wire  _GEN_27 = _GEN_0 | _GEN_13; // @[Decoupled.scala 47:20]
  wire  _GEN_28 = _GEN_1 | _GEN_14; // @[Decoupled.scala 47:20]
  wire  _GEN_29 = _GEN_2 | _GEN_15; // @[Decoupled.scala 47:20]
  wire  _GEN_30 = _GEN_3 | _GEN_16; // @[Decoupled.scala 47:20]
  wire  _GEN_39 = _T_22 | _T_15; // @[Router.scala 103:47]
  wire  _GEN_40 = _T_22 ? _GEN_27 : _GEN_13; // @[Router.scala 103:47]
  wire  _GEN_41 = _T_22 ? _GEN_28 : _GEN_14; // @[Router.scala 103:47]
  wire  _GEN_42 = _T_22 ? _GEN_29 : _GEN_15; // @[Router.scala 103:47]
  wire  _GEN_43 = _T_22 ? _GEN_30 : _GEN_16; // @[Router.scala 103:47]
  wire  _T_28 = tbl__T_13_data == 3'h2; // @[Router.scala 103:37]
  wire  _T_29 = io_outs_2_ready & _T_28; // @[Router.scala 103:29]
  wire  _GEN_55 = _GEN_0 | _GEN_40; // @[Decoupled.scala 47:20]
  wire  _GEN_56 = _GEN_1 | _GEN_41; // @[Decoupled.scala 47:20]
  wire  _GEN_57 = _GEN_2 | _GEN_42; // @[Decoupled.scala 47:20]
  wire  _GEN_58 = _GEN_3 | _GEN_43; // @[Decoupled.scala 47:20]
  wire  _GEN_67 = _T_29 | _GEN_39; // @[Router.scala 103:47]
  wire  _GEN_68 = _T_29 ? _GEN_55 : _GEN_40; // @[Router.scala 103:47]
  wire  _GEN_69 = _T_29 ? _GEN_56 : _GEN_41; // @[Router.scala 103:47]
  wire  _GEN_70 = _T_29 ? _GEN_57 : _GEN_42; // @[Router.scala 103:47]
  wire  _GEN_71 = _T_29 ? _GEN_58 : _GEN_43; // @[Router.scala 103:47]
  wire  _T_35 = tbl__T_13_data == 3'h3; // @[Router.scala 103:37]
  wire  _T_36 = io_outs_3_ready & _T_35; // @[Router.scala 103:29]
  wire  _GEN_83 = _GEN_0 | _GEN_68; // @[Decoupled.scala 47:20]
  wire  _GEN_84 = _GEN_1 | _GEN_69; // @[Decoupled.scala 47:20]
  wire  _GEN_85 = _GEN_2 | _GEN_70; // @[Decoupled.scala 47:20]
  wire  _GEN_86 = _GEN_3 | _GEN_71; // @[Decoupled.scala 47:20]
  wire  _GEN_95 = _T_36 | _GEN_67; // @[Router.scala 103:47]
  wire  _GEN_96 = _T_36 ? _GEN_83 : _GEN_68; // @[Router.scala 103:47]
  wire  _GEN_97 = _T_36 ? _GEN_84 : _GEN_69; // @[Router.scala 103:47]
  wire  _GEN_98 = _T_36 ? _GEN_85 : _GEN_70; // @[Router.scala 103:47]
  wire  _GEN_99 = _T_36 ? _GEN_86 : _GEN_71; // @[Router.scala 103:47]
  wire  _GEN_114 = io_in_valid & _GEN_95; // @[Router.scala 97:27]
  wire  _GEN_115 = io_in_valid & _GEN_96; // @[Router.scala 97:27]
  wire  _GEN_116 = io_in_valid & _GEN_97; // @[Router.scala 97:27]
  wire  _GEN_117 = io_in_valid & _GEN_98; // @[Router.scala 97:27]
  wire  _GEN_118 = io_in_valid & _GEN_99; // @[Router.scala 97:27]
  wire  _GEN_129 = io_in_valid & _T_15; // @[Router.scala 97:27]
  wire  _GEN_132 = io_in_valid & _T_22; // @[Router.scala 97:27]
  wire  _GEN_135 = io_in_valid & _T_29; // @[Router.scala 97:27]
  wire  _GEN_138 = io_in_valid & _T_36; // @[Router.scala 97:27]
  wire  _GEN_146 = io_load_routing_table_request_valid ? 1'h0 : io_in_valid; // @[Router.scala 91:51]
  wire  _GEN_147 = io_load_routing_table_request_valid ? 1'h0 : _GEN_114; // @[Router.scala 91:51]
  wire  _GEN_148 = io_load_routing_table_request_valid ? 1'h0 : _GEN_115; // @[Router.scala 91:51]
  wire  _GEN_149 = io_load_routing_table_request_valid ? 1'h0 : _GEN_116; // @[Router.scala 91:51]
  wire  _GEN_150 = io_load_routing_table_request_valid ? 1'h0 : _GEN_117; // @[Router.scala 91:51]
  wire  _GEN_151 = io_load_routing_table_request_valid ? 1'h0 : _GEN_118; // @[Router.scala 91:51]
  wire  _GEN_162 = io_load_routing_table_request_valid ? 1'h0 : _GEN_129; // @[Router.scala 91:51]
  wire  _GEN_165 = io_load_routing_table_request_valid ? 1'h0 : _GEN_132; // @[Router.scala 91:51]
  wire  _GEN_168 = io_load_routing_table_request_valid ? 1'h0 : _GEN_135; // @[Router.scala 91:51]
  wire  _GEN_171 = io_load_routing_table_request_valid ? 1'h0 : _GEN_138; // @[Router.scala 91:51]
  wire [2:0] _GEN_175 = _T_4 ? tbl__T_6_data : 3'h0; // @[Router.scala 86:84]
  wire  _GEN_222 = ~_T_4; // @[Router.scala 96:11]
  wire  _GEN_223 = _GEN_222 & io_load_routing_table_request_valid; // @[Router.scala 96:11]
  wire  _GEN_225 = ~io_load_routing_table_request_valid; // @[Router.scala 106:15]
  wire  _GEN_226 = _GEN_222 & _GEN_225; // @[Router.scala 106:15]
  wire  _GEN_227 = _GEN_226 & io_in_valid; // @[Router.scala 106:15]
  wire  _GEN_228 = _GEN_227 & _T_15; // @[Router.scala 106:15]
  wire  _GEN_233 = _GEN_227 & _T_22; // @[Router.scala 106:15]
  wire  _GEN_238 = _GEN_227 & _T_29; // @[Router.scala 106:15]
  wire  _GEN_243 = _GEN_227 & _T_36; // @[Router.scala 106:15]
  assign tbl__T_6_addr = io_read_routing_table_request_bits_addr[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_6_data = tbl[tbl__T_6_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_6_data = tbl__T_6_addr >= 4'hf ? _RAND_1[2:0] : tbl[tbl__T_6_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_13_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_13_data = tbl[tbl__T_13_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_13_data = tbl__T_13_addr >= 4'hf ? _RAND_2[2:0] : tbl[tbl__T_13_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_18_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_18_data = tbl[tbl__T_18_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_18_data = tbl__T_18_addr >= 4'hf ? _RAND_3[2:0] : tbl[tbl__T_18_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_25_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_25_data = tbl[tbl__T_25_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_25_data = tbl__T_25_addr >= 4'hf ? _RAND_4[2:0] : tbl[tbl__T_25_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_32_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_32_data = tbl[tbl__T_32_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_32_data = tbl__T_32_addr >= 4'hf ? _RAND_5[2:0] : tbl[tbl__T_32_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_39_addr = io_in_bits_header[3:0];
  `ifndef RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_39_data = tbl[tbl__T_39_addr]; // @[Router.scala 55:16]
  `else
  assign tbl__T_39_data = tbl__T_39_addr >= 4'hf ? _RAND_6[2:0] : tbl[tbl__T_39_addr]; // @[Router.scala 55:16]
  `endif // RANDOMIZE_GARBAGE_ASSIGN
  assign tbl__T_8_data = io_load_routing_table_request_bits_data[2:0];
  assign tbl__T_8_addr = io_load_routing_table_request_bits_addr[3:0];
  assign tbl__T_8_mask = 1'h1;
  assign tbl__T_8_en = _T_4 ? 1'h0 : io_load_routing_table_request_valid;
  assign io_read_routing_table_request_ready = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Decoupled.scala 72:20 Decoupled.scala 65:20]
  assign io_read_routing_table_response_valid = io_read_routing_table_request_valid & io_read_routing_table_response_ready; // @[Decoupled.scala 56:20 Decoupled.scala 47:20]
  assign io_read_routing_table_response_bits = {{29'd0}, _GEN_175}; // @[Router.scala 63:39 Decoupled.scala 48:19]
  assign io_load_routing_table_request_ready = _T_4 ? 1'h0 : io_load_routing_table_request_valid; // @[Decoupled.scala 72:20 Decoupled.scala 65:20]
  assign io_in_ready = _T_4 ? 1'h0 : _GEN_147; // @[Decoupled.scala 72:20 Decoupled.scala 65:20 Decoupled.scala 65:20 Decoupled.scala 65:20 Decoupled.scala 65:20]
  assign io_outs_0_valid = _T_4 ? 1'h0 : _GEN_148; // @[Decoupled.scala 56:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20]
  assign io_outs_0_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_0_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_1_valid = _T_4 ? 1'h0 : _GEN_149; // @[Decoupled.scala 56:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20]
  assign io_outs_1_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_1_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_2_valid = _T_4 ? 1'h0 : _GEN_150; // @[Decoupled.scala 56:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20]
  assign io_outs_2_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_2_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_3_valid = _T_4 ? 1'h0 : _GEN_151; // @[Decoupled.scala 56:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20 Decoupled.scala 47:20]
  assign io_outs_3_bits_header = io_in_bits_header; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
  assign io_outs_3_bits_body = io_in_bits_body; // @[Router.scala 67:14 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19 Decoupled.scala 48:19]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
  integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
  `ifdef RANDOMIZE
`ifdef INIT_RANDOM
   `INIT_RANDOM
`endif
`ifndef VERILATOR
   `ifdef RANDOMIZE_DELAY
      #`RANDOMIZE_DELAY begin end
   `else
      #0.002 begin end
   `endif
`endif
  _RAND_0 = {1{`RANDOM}};
  `ifdef RANDOMIZE_MEM_INIT
  for (initvar = 0; initvar < 15; initvar = initvar+1)
tbl[initvar] = _RAND_0[2:0];
  `endif // RANDOMIZE_MEM_INIT
  _RAND_1 = {1{`RANDOM}};
  _RAND_2 = {1{`RANDOM}};
  _RAND_3 = {1{`RANDOM}};
  _RAND_4 = {1{`RANDOM}};
  _RAND_5 = {1{`RANDOM}};
  _RAND_6 = {1{`RANDOM}};
  `endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
  always @(posedge clock) begin
if(tbl__T_8_en & tbl__T_8_mask) begin
   tbl[tbl__T_8_addr] <= tbl__T_8_data; // @[Router.scala 55:16]
end
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_223 & _T_10) begin
      $fwrite(32'h80000002,"setting tbl(%d) to %d\n",io_load_routing_table_request_bits_addr,io_load_routing_table_request_bits_data); // @[Router.scala 96:11]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_228 & _T_10) begin
      $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,io_in_bits_body,tbl__T_18_data); // @[Router.scala 106:15]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_233 & _T_10) begin
      $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,io_in_bits_body,tbl__T_25_data); // @[Router.scala 106:15]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_238 & _T_10) begin
      $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,io_in_bits_body,tbl__T_32_data); // @[Router.scala 106:15]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
`ifndef SYNTHESIS
`ifdef PRINTF_COND
   if (`PRINTF_COND) begin
`endif
      if (_GEN_243 & _T_10) begin
      $fwrite(32'h80000002,"got packet to route header %d, data %d, being routed to out(%d)\n",io_in_bits_header,io_in_bits_body,tbl__T_39_data); // @[Router.scala 106:15]
      end
`ifdef PRINTF_COND
   end
`endif
`endif // SYNTHESIS
  end
endmodule

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[经验] chisel中使用scala的循环与不使用循环的对比