chisel创建过滤链

joe

import chisel3._
import chisel3.util._

//抽象模块，只定义了接口
abstract class Filter[T <: Data](dtype:T) extends Module {
  val io = IO(new Bundle {
    //in为什么用Valid ??? 并且还用到了Input ???
    //Valid对象中有二个信号：
    // val valid = Output(Bool())
    // val bits = Output(gen)
    //但在前面用Input包裹了一层之后的in却在verilog代码中可以看到是
    // input        io_in_valid,
    // input  [3:0] io_in_bits,
    //val out = Output(Valid(chiselTypeOf(dtype)))这句表示在Output基础之后又用Output再定义了一次
    //结果在verilog中可以看到
    //output       io_out_valid,
    //output [3:0] io_out_bits
    val in = Input(Valid(chiselTypeOf(dtype))) //Valid接口只有output valid和bits，没有ready，即只有输出数据和输出有效指示
    val out = Output(Valid(chiselTypeOf(dtype)))
    //如果val in = Input(Output(Input(Valid(chiselTypeOf(dtype)))))产生的verilog代码一样，
    // 也就是说不管用多少层Input或Output包裹，最外的Input或Output才是最终的方向
    //另外，val in定义修改为：val in = Flipped(Valid(chiselTypeOf(dtype))) 产生的verilog代码也一样
  })
}
//谓词过滤需要有一个函数 即f:T=>Bool 参数
class PredicateFilter[T <: Data](dtype:T,f:T=>Bool) extends Filter(dtype) {
  io.out.valid := io.in.valid && f(dtype) //io.in.valid输入有效 同时还要谓词过滤也要有效
  io.out.bits := io.in.bits  //output到output赋值 ？？？？？ 并不是这样的，还是output data := input data
}
//创建过滤链
class SingleEvenFilter[T <: UInt](dtype:T) extends Filter(dtype) {
  val single = Module(new PredicateFilter(dtype,(x:T)=>x <= 9.U))
  val even = Module(new PredicateFilter(dtype,(x:T)=>x(0).asBool))  //最后一bit为1
  single.io.in <> io.in //不应该用“:=”而应该用“<>”整体连接符？？？实验发现用<>和:=产生的verilog代码完全一样(如果同一个接口中既有input又有output则两者效果应该不一样？),
  even.io.in <> single.io.out  //主要是因为父子模块级连，input连input，output连output
  io.out <> even.io.out
  //上面三句的作用就是：
  //模块的in接口(input valid,input bits)接到single.io.in接口 即模块in连到single的输入端口
  //even.io.in接口连到single.io.out接口 即even的输入端口连到single的输出端口
  //模块的输出连到even的输出
}

joe

Driver.execute(Array("--target-dir","generated"),()=>new SingleEvenFilter(10.U(4.W)))
产生的verilog代码如下：
module PredicateFilter(
  input  [3:0] io_in_bits,
  output [3:0] io_out_bits
);
  assign io_out_bits = io_in_bits; // @[SingleEvenFilter.scala 30:15]
endmodule
module PredicateFilter_1(
  input  [3:0] io_in_bits,
  output [3:0] io_out_bits
);
  assign io_out_bits = io_in_bits; // @[SingleEvenFilter.scala 30:15]
endmodule
module SingleEvenFilter(
  input        clock,
  input        reset,
  input        io_in_valid,
  input  [3:0] io_in_bits,
  output       io_out_valid,
  output [3:0] io_out_bits
);
  wire [3:0] single_io_in_bits; // @[SingleEvenFilter.scala 34:22]
  wire [3:0] single_io_out_bits; // @[SingleEvenFilter.scala 34:22]
  wire [3:0] even_io_in_bits; // @[SingleEvenFilter.scala 35:20]
  wire [3:0] even_io_out_bits; // @[SingleEvenFilter.scala 35:20]
  PredicateFilter single ( // @[SingleEvenFilter.scala 34:22]
    .io_in_bits(single_io_in_bits),
    .io_out_bits(single_io_out_bits)
  );
  PredicateFilter_1 even ( // @[SingleEvenFilter.scala 35:20]
    .io_in_bits(even_io_in_bits),
    .io_out_bits(even_io_out_bits)
  );
  assign io_out_valid = 1'h0; // @[SingleEvenFilter.scala 38:10]
  assign io_out_bits = even_io_out_bits; // @[SingleEvenFilter.scala 38:10]
  assign single_io_in_bits = io_in_bits; // @[SingleEvenFilter.scala 36:16]
  assign even_io_in_bits = single_io_out_bits; // @[SingleEvenFilter.scala 37:14]
endmodule

joe

如果是：Driver.execute(Array("--target-dir","generated"),()=>new SingleEvenFilter(3.U(4.W)))则产生的verilog内容如下：
module PredicateFilter(
  input        io_in_valid,
  input  [3:0] io_in_bits,
  output       io_out_valid,
  output [3:0] io_out_bits
);
  assign io_out_valid = io_in_valid; // @[SingleEvenFilter.scala 29:16]
  assign io_out_bits = io_in_bits; // @[SingleEvenFilter.scala 30:15]
endmodule
module PredicateFilter_1(
  input        io_in_valid,
  input  [3:0] io_in_bits,
  output       io_out_valid,
  output [3:0] io_out_bits
);
  assign io_out_valid = io_in_valid; // @[SingleEvenFilter.scala 29:16]
  assign io_out_bits = io_in_bits; // @[SingleEvenFilter.scala 30:15]
endmodule
module SingleEvenFilter(
  input        clock,
  input        reset,
  input        io_in_valid,
  input  [3:0] io_in_bits,
  output       io_out_valid,
  output [3:0] io_out_bits
);
  wire  single_io_in_valid; // @[SingleEvenFilter.scala 34:22]
  wire [3:0] single_io_in_bits; // @[SingleEvenFilter.scala 34:22]
  wire  single_io_out_valid; // @[SingleEvenFilter.scala 34:22]
  wire [3:0] single_io_out_bits; // @[SingleEvenFilter.scala 34:22]
  wire  even_io_in_valid; // @[SingleEvenFilter.scala 35:20]
  wire [3:0] even_io_in_bits; // @[SingleEvenFilter.scala 35:20]
  wire  even_io_out_valid; // @[SingleEvenFilter.scala 35:20]
  wire [3:0] even_io_out_bits; // @[SingleEvenFilter.scala 35:20]
  PredicateFilter single ( // @[SingleEvenFilter.scala 34:22]
    .io_in_valid(single_io_in_valid),
    .io_in_bits(single_io_in_bits),
    .io_out_valid(single_io_out_valid),
    .io_out_bits(single_io_out_bits)
  );
  PredicateFilter_1 even ( // @[SingleEvenFilter.scala 35:20]
    .io_in_valid(even_io_in_valid),
    .io_in_bits(even_io_in_bits),
    .io_out_valid(even_io_out_valid),
    .io_out_bits(even_io_out_bits)
  );
  assign io_out_valid = even_io_out_valid; // @[SingleEvenFilter.scala 38:10]
  assign io_out_bits = even_io_out_bits; // @[SingleEvenFilter.scala 38:10]
  assign single_io_in_valid = io_in_valid; // @[SingleEvenFilter.scala 36:16]
  assign single_io_in_bits = io_in_bits; // @[SingleEvenFilter.scala 36:16]
  assign even_io_in_valid = single_io_out_valid; // @[SingleEvenFilter.scala 37:14]
  assign even_io_in_bits = single_io_out_bits; // @[SingleEvenFilter.scala 37:14]
endmodule

joe

也就是说根据main中的参数，在f:T=>Bool参数处理结果不同的情况下，自动得出io.out.valid的不同结果值。