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楼主 |
发表于 2021-8-31 08:31:41
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生成的verilog代码如下:
module MealyFSM(
input clock,
input reset,
input io_din,
output io_risingEdge
);
reg stateReg; // @[MealyFSM.scala 14:25]
reg [31:0] _RAND_0;
wire _T = ~stateReg; // @[Conditional.scala 37:30]
wire _GEN_0 = io_din | stateReg; // @[MealyFSM.scala 20:20]
wire _T_2 = ~io_din; // @[MealyFSM.scala 29:12]
assign io_risingEdge = _T & io_din; // @[MealyFSM.scala 16:17 MealyFSM.scala 24:23 MealyFSM.scala 38:23]
always @(posedge clock) begin
if (reset) begin
stateReg <= 1'h0;
end else if (_T) begin
stateReg <= _GEN_0;
end else if (stateReg) begin
if (_T_2) begin
stateReg <= 1'h0;
end
end
end
endmodule
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