risc-v中文论坛 › Chisel › chisel中val/var,=和:=

joe 发表于 2021-8-10 16:15:31

chisel中val/var,=和:=

1）
import chisel3._
class FullAdder extends Module {
val io = IO(new Bundle {
    val a = Input(UInt(1.W))
        val b = Input(UInt(1.W))
        val cin = Input(UInt(1.W))
        val sum = Output(UInt(1.W))
        val cout = Output(UInt(1.W))
})
val a_xor_b = io.a ^ io.b
io.sum := a_xor_b ^ io.cin
//上面代码产生sum
//下面代码产生进位
val a_and_b = io.a & io.b
val b_and_cin = io.b & io.cin
val a_and_cin = io.a & io_cin
io.cout := a_and_b | b_and_cin | a_and_cin
}
上面代码是OK，下面代码：
2）
class FullAdder extends Module {
val io = IO(new Bundle {
    val a = Input(UInt(1.W))
        val b = Input(UInt(1.W))
        val cin = Input(UInt(1.W))
        val sum = Output(UInt(1.W))
        val cout = Output(UInt(1.W))
})
val a_xor_b = io.a ^ io.b
io.sum = a_xor_b ^ io.cin
//上面代码产生sum
//下面代码产生进位
val a_and_b = io.a & io.b
val b_and_cin = io.b & io.cin
val a_and_cin = io.a & io_cin
io.cout := a_and_b | b_and_cin | a_and_cin
}
则语法错误，那下面代码：
3）
class FullAdder extends Module {
val io = IO(new Bundle {
    val a = Input(UInt(1.W))
        val b = Input(UInt(1.W))
        val cin = Input(UInt(1.W))
        var sum = Output(UInt(1.W))
        val cout = Output(UInt(1.W))
})
val a_xor_b = io.a ^ io.b
io.sum := a_xor_b ^ io.cin
//上面代码产生sum
//下面代码产生进位
val a_and_b = io.a & io.b
val b_and_cin = io.b & io.cin
val a_and_cin = io.a & io_cin
io.cout := a_and_b | b_and_cin | a_and_cin
}
则也OK，但与1）相比较有什么不同？
4）
class FullAdder extends Module {
val io = IO(new Bundle {
    val a = Input(UInt(1.W))
        val b = Input(UInt(1.W))
        val cin = Input(UInt(1.W))
        var sum = Output(UInt(1.W))
        val cout = Output(UInt(1.W))
})
val a_xor_b = io.a ^ io.b
io.sum = a_xor_b ^ io.cin
//上面代码产生sum
//下面代码产生进位
val a_and_b = io.a & io.b
val b_and_cin = io.b & io.cin
val a_and_cin = io.a & io_cin
io.cout := a_and_b | b_and_cin | a_and_cin
}
代码和3）比较起来又有什么不同？

joe 发表于 2021-8-12 15:15:28

针对上面，做几个实验，实验一：
代码是：
val sum = Output(UInt(1.W))
io.sum := a_xor_b ^ io.cin
时的.fir和verilog代码分别如下：
;buildInfoPackage: chisel3, version: 3.1.2, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-07-25 16:52:17.431, builtAtMillis: 1532537537431
circuit Adder :
module FullAdder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_1 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_2 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_3 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_4 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_5 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_6 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_7 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module Adder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip A : UInt<8>, flip B : UInt<8>, flip Cin : UInt<1>, Sum : UInt<8>, Cout : UInt<1>}

    inst FullAdder of FullAdder @
    FullAdder.clock <= clock
    FullAdder.reset <= reset
    inst FullAdder_1 of FullAdder_1 @
    FullAdder_1.clock <= clock
    FullAdder_1.reset <= reset
    inst FullAdder_2 of FullAdder_2 @
    FullAdder_2.clock <= clock
    FullAdder_2.reset <= reset
    inst FullAdder_3 of FullAdder_3 @
    FullAdder_3.clock <= clock
    FullAdder_3.reset <= reset
    inst FullAdder_4 of FullAdder_4 @
    FullAdder_4.clock <= clock
    FullAdder_4.reset <= reset
    inst FullAdder_5 of FullAdder_5 @
    FullAdder_5.clock <= clock
    FullAdder_5.reset <= reset
    inst FullAdder_6 of FullAdder_6 @
    FullAdder_6.clock <= clock
    FullAdder_6.reset <= reset
    inst FullAdder_7 of FullAdder_7 @
    FullAdder_7.clock <= clock
    FullAdder_7.reset <= reset
    wire carry : UInt<1> @
    wire sum : UInt<1> @
    carry <= io.Cin @
    node _T_42 = bits(io.A, 0, 0) @
    FullAdder.io.a <= _T_42 @
    node _T_43 = bits(io.B, 0, 0) @
    FullAdder.io.b <= _T_43 @
    FullAdder.io.cin <= carry @
    carry <= FullAdder.io.cout @
    node _T_44 = bits(FullAdder.io.sum, 0, 0) @
    sum <= _T_44 @
    node _T_45 = bits(io.A, 1, 1) @
    FullAdder_1.io.a <= _T_45 @
    node _T_46 = bits(io.B, 1, 1) @
    FullAdder_1.io.b <= _T_46 @
    FullAdder_1.io.cin <= carry @
    carry <= FullAdder_1.io.cout @
    node _T_47 = bits(FullAdder_1.io.sum, 0, 0) @
    sum <= _T_47 @
    node _T_48 = bits(io.A, 2, 2) @
    FullAdder_2.io.a <= _T_48 @
    node _T_49 = bits(io.B, 2, 2) @
    FullAdder_2.io.b <= _T_49 @
    FullAdder_2.io.cin <= carry @
    carry <= FullAdder_2.io.cout @
    node _T_50 = bits(FullAdder_2.io.sum, 0, 0) @
    sum <= _T_50 @
    node _T_51 = bits(io.A, 3, 3) @
    FullAdder_3.io.a <= _T_51 @
    node _T_52 = bits(io.B, 3, 3) @
    FullAdder_3.io.b <= _T_52 @
    FullAdder_3.io.cin <= carry @
    carry <= FullAdder_3.io.cout @
    node _T_53 = bits(FullAdder_3.io.sum, 0, 0) @
    sum <= _T_53 @
    node _T_54 = bits(io.A, 4, 4) @
    FullAdder_4.io.a <= _T_54 @
    node _T_55 = bits(io.B, 4, 4) @
    FullAdder_4.io.b <= _T_55 @
    FullAdder_4.io.cin <= carry @
    carry <= FullAdder_4.io.cout @
    node _T_56 = bits(FullAdder_4.io.sum, 0, 0) @
    sum <= _T_56 @
    node _T_57 = bits(io.A, 5, 5) @
    FullAdder_5.io.a <= _T_57 @
    node _T_58 = bits(io.B, 5, 5) @
    FullAdder_5.io.b <= _T_58 @
    FullAdder_5.io.cin <= carry @
    carry <= FullAdder_5.io.cout @
    node _T_59 = bits(FullAdder_5.io.sum, 0, 0) @
    sum <= _T_59 @
    node _T_60 = bits(io.A, 6, 6) @
    FullAdder_6.io.a <= _T_60 @
    node _T_61 = bits(io.B, 6, 6) @
    FullAdder_6.io.b <= _T_61 @
    FullAdder_6.io.cin <= carry @
    carry <= FullAdder_6.io.cout @
    node _T_62 = bits(FullAdder_6.io.sum, 0, 0) @
    sum <= _T_62 @
    node _T_63 = bits(io.A, 7, 7) @
    FullAdder_7.io.a <= _T_63 @
    node _T_64 = bits(io.B, 7, 7) @
    FullAdder_7.io.b <= _T_64 @
    FullAdder_7.io.cin <= carry @
    carry <= FullAdder_7.io.cout @
    node _T_65 = bits(FullAdder_7.io.sum, 0, 0) @
    sum <= _T_65 @
    node _T_66 = cat(sum, sum) @
    node _T_67 = cat(sum, sum) @
    node _T_68 = cat(_T_67, _T_66) @
    node _T_69 = cat(sum, sum) @
    node _T_70 = cat(sum, sum) @
    node _T_71 = cat(_T_70, _T_69) @
    node _T_72 = cat(_T_71, _T_68) @
    io.Sum <= _T_72 @
    io.Cout <= carry @

joe 发表于 2021-8-12 15:16:05

module FullAdder( // @[:@3.2]
input   io_a, // @[:@6.4]
input   io_b, // @[:@6.4]
input   io_cin, // @[:@6.4]
outputio_sum, // @[:@6.4]
outputio_cout // @[:@6.4]
);
wirea_xor_b; // @
wirea_and_b; // @
wireb_and_cin; // @
wirea_and_cin; // @
wire_T_16; // @
assign a_xor_b = io_a ^ io_b; // @
assign a_and_b = io_a & io_b; // @
assign b_and_cin = io_b & io_cin; // @
assign a_and_cin = io_a & io_cin; // @
assign _T_16 = a_and_b | b_and_cin; // @
assign io_sum = a_xor_b ^ io_cin; // @
assign io_cout = _T_16 | a_and_cin; // @
endmodule
module Adder( // @[:@123.2]
input      clock, // @[:@124.4]
input      reset, // @[:@125.4]
input io_A, // @[:@126.4]
input io_B, // @[:@126.4]
input      io_Cin, // @[:@126.4]
output io_Sum, // @[:@126.4]
output       io_Cout // @[:@126.4]
);
wireFullAdder_io_a; // @
wireFullAdder_io_b; // @
wireFullAdder_io_cin; // @
wireFullAdder_io_sum; // @
wireFullAdder_io_cout; // @
wireFullAdder_1_io_a; // @
wireFullAdder_1_io_b; // @
wireFullAdder_1_io_cin; // @
wireFullAdder_1_io_sum; // @
wireFullAdder_1_io_cout; // @
wireFullAdder_2_io_a; // @
wireFullAdder_2_io_b; // @
wireFullAdder_2_io_cin; // @
wireFullAdder_2_io_sum; // @
wireFullAdder_2_io_cout; // @
wireFullAdder_3_io_a; // @
wireFullAdder_3_io_b; // @
wireFullAdder_3_io_cin; // @
wireFullAdder_3_io_sum; // @
wireFullAdder_3_io_cout; // @
wireFullAdder_4_io_a; // @
wireFullAdder_4_io_b; // @
wireFullAdder_4_io_cin; // @
wireFullAdder_4_io_sum; // @
wireFullAdder_4_io_cout; // @
wireFullAdder_5_io_a; // @
wireFullAdder_5_io_b; // @
wireFullAdder_5_io_cin; // @
wireFullAdder_5_io_sum; // @
wireFullAdder_5_io_cout; // @
wireFullAdder_6_io_a; // @
wireFullAdder_6_io_b; // @
wireFullAdder_6_io_cin; // @
wireFullAdder_6_io_sum; // @
wireFullAdder_6_io_cout; // @
wireFullAdder_7_io_a; // @
wireFullAdder_7_io_b; // @
wireFullAdder_7_io_cin; // @
wireFullAdder_7_io_sum; // @
wireFullAdder_7_io_cout; // @
wiresum_0; // @
wiresum_1; // @
wiresum_2; // @
wiresum_3; // @
wiresum_4; // @
wiresum_5; // @
wiresum_6; // @
wiresum_7; // @
wire _T_66; // @
wire _T_67; // @
wire _T_68; // @
wire _T_69; // @
wire _T_70; // @
wire _T_71; // @
FullAdder FullAdder ( // @
    .io_a(FullAdder_io_a),
    .io_b(FullAdder_io_b),
    .io_cin(FullAdder_io_cin),
    .io_sum(FullAdder_io_sum),
    .io_cout(FullAdder_io_cout)
);
FullAdder FullAdder_1 ( // @
    .io_a(FullAdder_1_io_a),
    .io_b(FullAdder_1_io_b),
    .io_cin(FullAdder_1_io_cin),
    .io_sum(FullAdder_1_io_sum),
    .io_cout(FullAdder_1_io_cout)
);
FullAdder FullAdder_2 ( // @
    .io_a(FullAdder_2_io_a),
    .io_b(FullAdder_2_io_b),
    .io_cin(FullAdder_2_io_cin),
    .io_sum(FullAdder_2_io_sum),
    .io_cout(FullAdder_2_io_cout)
);
FullAdder FullAdder_3 ( // @
    .io_a(FullAdder_3_io_a),
    .io_b(FullAdder_3_io_b),
    .io_cin(FullAdder_3_io_cin),
    .io_sum(FullAdder_3_io_sum),
    .io_cout(FullAdder_3_io_cout)
);
FullAdder FullAdder_4 ( // @
    .io_a(FullAdder_4_io_a),
    .io_b(FullAdder_4_io_b),
    .io_cin(FullAdder_4_io_cin),
    .io_sum(FullAdder_4_io_sum),
    .io_cout(FullAdder_4_io_cout)
);
FullAdder FullAdder_5 ( // @
    .io_a(FullAdder_5_io_a),
    .io_b(FullAdder_5_io_b),
    .io_cin(FullAdder_5_io_cin),
    .io_sum(FullAdder_5_io_sum),
    .io_cout(FullAdder_5_io_cout)
);
FullAdder FullAdder_6 ( // @
    .io_a(FullAdder_6_io_a),
    .io_b(FullAdder_6_io_b),
    .io_cin(FullAdder_6_io_cin),
    .io_sum(FullAdder_6_io_sum),
    .io_cout(FullAdder_6_io_cout)
);
FullAdder FullAdder_7 ( // @
    .io_a(FullAdder_7_io_a),
    .io_b(FullAdder_7_io_b),
    .io_cin(FullAdder_7_io_cin),
    .io_sum(FullAdder_7_io_sum),
    .io_cout(FullAdder_7_io_cout)
);
assign sum_0 = FullAdder_io_sum; // @
assign sum_1 = FullAdder_1_io_sum; // @
assign sum_2 = FullAdder_2_io_sum; // @
assign sum_3 = FullAdder_3_io_sum; // @
assign sum_4 = FullAdder_4_io_sum; // @
assign sum_5 = FullAdder_5_io_sum; // @
assign sum_6 = FullAdder_6_io_sum; // @
assign sum_7 = FullAdder_7_io_sum; // @
assign _T_66 = {sum_1,sum_0}; // @
assign _T_67 = {sum_3,sum_2}; // @
assign _T_68 = {_T_67,_T_66}; // @
assign _T_69 = {sum_5,sum_4}; // @
assign _T_70 = {sum_7,sum_6}; // @
assign _T_71 = {_T_70,_T_69}; // @
assign io_Sum = {_T_71,_T_68}; // @
assign io_Cout = FullAdder_7_io_cout; // @
assign FullAdder_io_a = io_A; // @
assign FullAdder_io_b = io_B; // @
assign FullAdder_io_cin = io_Cin; // @
assign FullAdder_1_io_a = io_A; // @
assign FullAdder_1_io_b = io_B; // @
assign FullAdder_1_io_cin = FullAdder_io_cout; // @
assign FullAdder_2_io_a = io_A; // @
assign FullAdder_2_io_b = io_B; // @
assign FullAdder_2_io_cin = FullAdder_1_io_cout; // @
assign FullAdder_3_io_a = io_A; // @
assign FullAdder_3_io_b = io_B; // @
assign FullAdder_3_io_cin = FullAdder_2_io_cout; // @
assign FullAdder_4_io_a = io_A; // @
assign FullAdder_4_io_b = io_B; // @
assign FullAdder_4_io_cin = FullAdder_3_io_cout; // @
assign FullAdder_5_io_a = io_A; // @
assign FullAdder_5_io_b = io_B; // @
assign FullAdder_5_io_cin = FullAdder_4_io_cout; // @
assign FullAdder_6_io_a = io_A; // @
assign FullAdder_6_io_b = io_B; // @
assign FullAdder_6_io_cin = FullAdder_5_io_cout; // @
assign FullAdder_7_io_a = io_A; // @
assign FullAdder_7_io_b = io_B; // @
assign FullAdder_7_io_cin = FullAdder_6_io_cout; // @
endmodule

joe 发表于 2021-8-12 15:16:54

实验二：
如果是
var sum = Output(UInt(1.W))
io.sum = a_xor_b ^ io.cin
则编译能成功，能产生.fir文件（见下面），但run或debug则出现：
firrtl.passes.CheckChirrtl$UndeclaredReferenceException:@: Reference _T_15 is not declared
因为出现错误，当然也不会产生verilog文件了
通过上句错误提示结合下面.fir文件内容和FullAdder.scala源代码可知就是io.sum = a_xor_b ^ io.cin这句有问题？为什么呢？？？？
.fir文件内容如下：
;buildInfoPackage: chisel3, version: 3.1.2, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-07-25 16:52:17.431, builtAtMillis: 1532537537431
circuit Adder :
module FullAdder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_1 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_2 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_3 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_4 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_5 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_6 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_7 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module Adder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip A : UInt<8>, flip B : UInt<8>, flip Cin : UInt<1>, Sum : UInt<8>, Cout : UInt<1>}

    inst FullAdder of FullAdder @
    FullAdder.clock <= clock
    FullAdder.reset <= reset
    inst FullAdder_1 of FullAdder_1 @
    FullAdder_1.clock <= clock
    FullAdder_1.reset <= reset
    inst FullAdder_2 of FullAdder_2 @
    FullAdder_2.clock <= clock
    FullAdder_2.reset <= reset
    inst FullAdder_3 of FullAdder_3 @
    FullAdder_3.clock <= clock
    FullAdder_3.reset <= reset
    inst FullAdder_4 of FullAdder_4 @
    FullAdder_4.clock <= clock
    FullAdder_4.reset <= reset
    inst FullAdder_5 of FullAdder_5 @
    FullAdder_5.clock <= clock
    FullAdder_5.reset <= reset
    inst FullAdder_6 of FullAdder_6 @
    FullAdder_6.clock <= clock
    FullAdder_6.reset <= reset
    inst FullAdder_7 of FullAdder_7 @
    FullAdder_7.clock <= clock
    FullAdder_7.reset <= reset
    wire carry : UInt<1> @
    wire sum : UInt<1> @
    carry <= io.Cin @
    node _T_42 = bits(io.A, 0, 0) @
    FullAdder.io.a <= _T_42 @
    node _T_43 = bits(io.B, 0, 0) @
    FullAdder.io.b <= _T_43 @
    FullAdder.io.cin <= carry @
    carry <= FullAdder.io.cout @
    node _T_44 = bits(_T_15, 0, 0) @
    sum <= _T_44 @
    node _T_45 = bits(io.A, 1, 1) @
    FullAdder_1.io.a <= _T_45 @
    node _T_46 = bits(io.B, 1, 1) @
    FullAdder_1.io.b <= _T_46 @
    FullAdder_1.io.cin <= carry @
    carry <= FullAdder_1.io.cout @
    node _T_47 = bits(_T_15, 0, 0) @
    sum <= _T_47 @
    node _T_48 = bits(io.A, 2, 2) @
    FullAdder_2.io.a <= _T_48 @
    node _T_49 = bits(io.B, 2, 2) @
    FullAdder_2.io.b <= _T_49 @
    FullAdder_2.io.cin <= carry @
    carry <= FullAdder_2.io.cout @
    node _T_50 = bits(_T_15, 0, 0) @
    sum <= _T_50 @
    node _T_51 = bits(io.A, 3, 3) @
    FullAdder_3.io.a <= _T_51 @
    node _T_52 = bits(io.B, 3, 3) @
    FullAdder_3.io.b <= _T_52 @
    FullAdder_3.io.cin <= carry @
    carry <= FullAdder_3.io.cout @
    node _T_53 = bits(_T_15, 0, 0) @
    sum <= _T_53 @
    node _T_54 = bits(io.A, 4, 4) @
    FullAdder_4.io.a <= _T_54 @
    node _T_55 = bits(io.B, 4, 4) @
    FullAdder_4.io.b <= _T_55 @
    FullAdder_4.io.cin <= carry @
    carry <= FullAdder_4.io.cout @
    node _T_56 = bits(_T_15, 0, 0) @
    sum <= _T_56 @
    node _T_57 = bits(io.A, 5, 5) @
    FullAdder_5.io.a <= _T_57 @
    node _T_58 = bits(io.B, 5, 5) @
    FullAdder_5.io.b <= _T_58 @
    FullAdder_5.io.cin <= carry @
    carry <= FullAdder_5.io.cout @
    node _T_59 = bits(_T_15, 0, 0) @
    sum <= _T_59 @
    node _T_60 = bits(io.A, 6, 6) @
    FullAdder_6.io.a <= _T_60 @
    node _T_61 = bits(io.B, 6, 6) @
    FullAdder_6.io.b <= _T_61 @
    FullAdder_6.io.cin <= carry @
    carry <= FullAdder_6.io.cout @
    node _T_62 = bits(_T_15, 0, 0) @
    sum <= _T_62 @
    node _T_63 = bits(io.A, 7, 7) @
    FullAdder_7.io.a <= _T_63 @
    node _T_64 = bits(io.B, 7, 7) @
    FullAdder_7.io.b <= _T_64 @
    FullAdder_7.io.cin <= carry @
    carry <= FullAdder_7.io.cout @
    node _T_65 = bits(_T_15, 0, 0) @
    sum <= _T_65 @
    node _T_66 = cat(sum, sum) @
    node _T_67 = cat(sum, sum) @
    node _T_68 = cat(_T_67, _T_66) @
    node _T_69 = cat(sum, sum) @
    node _T_70 = cat(sum, sum) @
    node _T_71 = cat(_T_70, _T_69) @
    node _T_72 = cat(_T_71, _T_68) @
    io.Sum <= _T_72 @
    io.Cout <= carry @
很明显地看到，fir文件中没有io.sum <= _T_15

joe 发表于 2021-8-12 15:18:05

实验三：
如果是
var sum = Output(UInt(1.W))
io.sum := a_xor_b ^ io.cin
run/debug之后，.fir文件如下：
;buildInfoPackage: chisel3, version: 3.1.2, scalaVersion: 2.11.12, sbtVersion: 1.1.1, builtAtString: 2018-07-25 16:52:17.431, builtAtMillis: 1532537537431
circuit Adder :
module FullAdder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_1 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_2 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_3 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_4 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_5 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_6 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module FullAdder_7 :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : UInt<1>, flip b : UInt<1>, flip cin : UInt<1>, sum : UInt<1>, cout : UInt<1>}

    node a_xor_b = xor(io.a, io.b) @
    node _T_15 = xor(a_xor_b, io.cin) @
    io.sum <= _T_15 @
    node a_and_b = and(io.a, io.b) @
    node b_and_cin = and(io.b, io.cin) @
    node a_and_cin = and(io.a, io.cin) @
    node _T_16 = or(a_and_b, b_and_cin) @
    node _T_17 = or(_T_16, a_and_cin) @
    io.cout <= _T_17 @

module Adder :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip A : UInt<8>, flip B : UInt<8>, flip Cin : UInt<1>, Sum : UInt<8>, Cout : UInt<1>}

    inst FullAdder of FullAdder @
    FullAdder.clock <= clock
    FullAdder.reset <= reset
    inst FullAdder_1 of FullAdder_1 @
    FullAdder_1.clock <= clock
    FullAdder_1.reset <= reset
    inst FullAdder_2 of FullAdder_2 @
    FullAdder_2.clock <= clock
    FullAdder_2.reset <= reset
    inst FullAdder_3 of FullAdder_3 @
    FullAdder_3.clock <= clock
    FullAdder_3.reset <= reset
    inst FullAdder_4 of FullAdder_4 @
    FullAdder_4.clock <= clock
    FullAdder_4.reset <= reset
    inst FullAdder_5 of FullAdder_5 @
    FullAdder_5.clock <= clock
    FullAdder_5.reset <= reset
    inst FullAdder_6 of FullAdder_6 @
    FullAdder_6.clock <= clock
    FullAdder_6.reset <= reset
    inst FullAdder_7 of FullAdder_7 @
    FullAdder_7.clock <= clock
    FullAdder_7.reset <= reset
    wire carry : UInt<1> @
    wire sum : UInt<1> @
    carry <= io.Cin @
    node _T_42 = bits(io.A, 0, 0) @
    FullAdder.io.a <= _T_42 @
    node _T_43 = bits(io.B, 0, 0) @
    FullAdder.io.b <= _T_43 @
    FullAdder.io.cin <= carry @
    carry <= FullAdder.io.cout @
    node _T_44 = bits(FullAdder.io.sum, 0, 0) @
    sum <= _T_44 @
    node _T_45 = bits(io.A, 1, 1) @
    FullAdder_1.io.a <= _T_45 @
    node _T_46 = bits(io.B, 1, 1) @
    FullAdder_1.io.b <= _T_46 @
    FullAdder_1.io.cin <= carry @
    carry <= FullAdder_1.io.cout @
    node _T_47 = bits(FullAdder_1.io.sum, 0, 0) @
    sum <= _T_47 @
    node _T_48 = bits(io.A, 2, 2) @
    FullAdder_2.io.a <= _T_48 @
    node _T_49 = bits(io.B, 2, 2) @
    FullAdder_2.io.b <= _T_49 @
    FullAdder_2.io.cin <= carry @
    carry <= FullAdder_2.io.cout @
    node _T_50 = bits(FullAdder_2.io.sum, 0, 0) @
    sum <= _T_50 @
    node _T_51 = bits(io.A, 3, 3) @
    FullAdder_3.io.a <= _T_51 @
    node _T_52 = bits(io.B, 3, 3) @
    FullAdder_3.io.b <= _T_52 @
    FullAdder_3.io.cin <= carry @
    carry <= FullAdder_3.io.cout @
    node _T_53 = bits(FullAdder_3.io.sum, 0, 0) @
    sum <= _T_53 @
    node _T_54 = bits(io.A, 4, 4) @
    FullAdder_4.io.a <= _T_54 @
    node _T_55 = bits(io.B, 4, 4) @
    FullAdder_4.io.b <= _T_55 @
    FullAdder_4.io.cin <= carry @
    carry <= FullAdder_4.io.cout @
    node _T_56 = bits(FullAdder_4.io.sum, 0, 0) @
    sum <= _T_56 @
    node _T_57 = bits(io.A, 5, 5) @
    FullAdder_5.io.a <= _T_57 @
    node _T_58 = bits(io.B, 5, 5) @
    FullAdder_5.io.b <= _T_58 @
    FullAdder_5.io.cin <= carry @
    carry <= FullAdder_5.io.cout @
    node _T_59 = bits(FullAdder_5.io.sum, 0, 0) @
    sum <= _T_59 @
    node _T_60 = bits(io.A, 6, 6) @
    FullAdder_6.io.a <= _T_60 @
    node _T_61 = bits(io.B, 6, 6) @
    FullAdder_6.io.b <= _T_61 @
    FullAdder_6.io.cin <= carry @
    carry <= FullAdder_6.io.cout @
    node _T_62 = bits(FullAdder_6.io.sum, 0, 0) @
    sum <= _T_62 @
    node _T_63 = bits(io.A, 7, 7) @
    FullAdder_7.io.a <= _T_63 @
    node _T_64 = bits(io.B, 7, 7) @
    FullAdder_7.io.b <= _T_64 @
    FullAdder_7.io.cin <= carry @
    carry <= FullAdder_7.io.cout @
    node _T_65 = bits(FullAdder_7.io.sum, 0, 0) @
    sum <= _T_65 @
    node _T_66 = cat(sum, sum) @
    node _T_67 = cat(sum, sum) @
    node _T_68 = cat(_T_67, _T_66) @
    node _T_69 = cat(sum, sum) @
    node _T_70 = cat(sum, sum) @
    node _T_71 = cat(_T_70, _T_69) @
    node _T_72 = cat(_T_71, _T_68) @
    io.Sum <= _T_72 @
    io.Cout <= carry @

joe 发表于 2021-8-12 15:18:34

verilog文件如下：
module FullAdder( // @[:@3.2]
input   io_a, // @[:@6.4]
input   io_b, // @[:@6.4]
input   io_cin, // @[:@6.4]
outputio_sum, // @[:@6.4]
outputio_cout // @[:@6.4]
);
wirea_xor_b; // @
wirea_and_b; // @
wireb_and_cin; // @
wirea_and_cin; // @
wire_T_16; // @
assign a_xor_b = io_a ^ io_b; // @
assign a_and_b = io_a & io_b; // @
assign b_and_cin = io_b & io_cin; // @
assign a_and_cin = io_a & io_cin; // @
assign _T_16 = a_and_b | b_and_cin; // @
assign io_sum = a_xor_b ^ io_cin; // @
assign io_cout = _T_16 | a_and_cin; // @
endmodule
module Adder( // @[:@123.2]
input      clock, // @[:@124.4]
input      reset, // @[:@125.4]
input io_A, // @[:@126.4]
input io_B, // @[:@126.4]
input      io_Cin, // @[:@126.4]
output io_Sum, // @[:@126.4]
output       io_Cout // @[:@126.4]
);
wireFullAdder_io_a; // @
wireFullAdder_io_b; // @
wireFullAdder_io_cin; // @
wireFullAdder_io_sum; // @
wireFullAdder_io_cout; // @
wireFullAdder_1_io_a; // @
wireFullAdder_1_io_b; // @
wireFullAdder_1_io_cin; // @
wireFullAdder_1_io_sum; // @
wireFullAdder_1_io_cout; // @
wireFullAdder_2_io_a; // @
wireFullAdder_2_io_b; // @
wireFullAdder_2_io_cin; // @
wireFullAdder_2_io_sum; // @
wireFullAdder_2_io_cout; // @
wireFullAdder_3_io_a; // @
wireFullAdder_3_io_b; // @
wireFullAdder_3_io_cin; // @
wireFullAdder_3_io_sum; // @
wireFullAdder_3_io_cout; // @
wireFullAdder_4_io_a; // @
wireFullAdder_4_io_b; // @
wireFullAdder_4_io_cin; // @
wireFullAdder_4_io_sum; // @
wireFullAdder_4_io_cout; // @
wireFullAdder_5_io_a; // @
wireFullAdder_5_io_b; // @
wireFullAdder_5_io_cin; // @
wireFullAdder_5_io_sum; // @
wireFullAdder_5_io_cout; // @
wireFullAdder_6_io_a; // @
wireFullAdder_6_io_b; // @
wireFullAdder_6_io_cin; // @
wireFullAdder_6_io_sum; // @
wireFullAdder_6_io_cout; // @
wireFullAdder_7_io_a; // @
wireFullAdder_7_io_b; // @
wireFullAdder_7_io_cin; // @
wireFullAdder_7_io_sum; // @
wireFullAdder_7_io_cout; // @
wiresum_0; // @
wiresum_1; // @
wiresum_2; // @
wiresum_3; // @
wiresum_4; // @
wiresum_5; // @
wiresum_6; // @
wiresum_7; // @
wire _T_66; // @
wire _T_67; // @
wire _T_68; // @
wire _T_69; // @
wire _T_70; // @
wire _T_71; // @
FullAdder FullAdder ( // @
    .io_a(FullAdder_io_a),
    .io_b(FullAdder_io_b),
    .io_cin(FullAdder_io_cin),
    .io_sum(FullAdder_io_sum),
    .io_cout(FullAdder_io_cout)
);
FullAdder FullAdder_1 ( // @
    .io_a(FullAdder_1_io_a),
    .io_b(FullAdder_1_io_b),
    .io_cin(FullAdder_1_io_cin),
    .io_sum(FullAdder_1_io_sum),
    .io_cout(FullAdder_1_io_cout)
);
FullAdder FullAdder_2 ( // @
    .io_a(FullAdder_2_io_a),
    .io_b(FullAdder_2_io_b),
    .io_cin(FullAdder_2_io_cin),
    .io_sum(FullAdder_2_io_sum),
    .io_cout(FullAdder_2_io_cout)
);
FullAdder FullAdder_3 ( // @
    .io_a(FullAdder_3_io_a),
    .io_b(FullAdder_3_io_b),
    .io_cin(FullAdder_3_io_cin),
    .io_sum(FullAdder_3_io_sum),
    .io_cout(FullAdder_3_io_cout)
);
FullAdder FullAdder_4 ( // @
    .io_a(FullAdder_4_io_a),
    .io_b(FullAdder_4_io_b),
    .io_cin(FullAdder_4_io_cin),
    .io_sum(FullAdder_4_io_sum),
    .io_cout(FullAdder_4_io_cout)
);
FullAdder FullAdder_5 ( // @
    .io_a(FullAdder_5_io_a),
    .io_b(FullAdder_5_io_b),
    .io_cin(FullAdder_5_io_cin),
    .io_sum(FullAdder_5_io_sum),
    .io_cout(FullAdder_5_io_cout)
);
FullAdder FullAdder_6 ( // @
    .io_a(FullAdder_6_io_a),
    .io_b(FullAdder_6_io_b),
    .io_cin(FullAdder_6_io_cin),
    .io_sum(FullAdder_6_io_sum),
    .io_cout(FullAdder_6_io_cout)
);
FullAdder FullAdder_7 ( // @
    .io_a(FullAdder_7_io_a),
    .io_b(FullAdder_7_io_b),
    .io_cin(FullAdder_7_io_cin),
    .io_sum(FullAdder_7_io_sum),
    .io_cout(FullAdder_7_io_cout)
);
assign sum_0 = FullAdder_io_sum; // @
assign sum_1 = FullAdder_1_io_sum; // @
assign sum_2 = FullAdder_2_io_sum; // @
assign sum_3 = FullAdder_3_io_sum; // @
assign sum_4 = FullAdder_4_io_sum; // @
assign sum_5 = FullAdder_5_io_sum; // @
assign sum_6 = FullAdder_6_io_sum; // @
assign sum_7 = FullAdder_7_io_sum; // @
assign _T_66 = {sum_1,sum_0}; // @
assign _T_67 = {sum_3,sum_2}; // @
assign _T_68 = {_T_67,_T_66}; // @
assign _T_69 = {sum_5,sum_4}; // @
assign _T_70 = {sum_7,sum_6}; // @
assign _T_71 = {_T_70,_T_69}; // @
assign io_Sum = {_T_71,_T_68}; // @
assign io_Cout = FullAdder_7_io_cout; // @
assign FullAdder_io_a = io_A; // @
assign FullAdder_io_b = io_B; // @
assign FullAdder_io_cin = io_Cin; // @
assign FullAdder_1_io_a = io_A; // @
assign FullAdder_1_io_b = io_B; // @
assign FullAdder_1_io_cin = FullAdder_io_cout; // @
assign FullAdder_2_io_a = io_A; // @
assign FullAdder_2_io_b = io_B; // @
assign FullAdder_2_io_cin = FullAdder_1_io_cout; // @
assign FullAdder_3_io_a = io_A; // @
assign FullAdder_3_io_b = io_B; // @
assign FullAdder_3_io_cin = FullAdder_2_io_cout; // @
assign FullAdder_4_io_a = io_A; // @
assign FullAdder_4_io_b = io_B; // @
assign FullAdder_4_io_cin = FullAdder_3_io_cout; // @
assign FullAdder_5_io_a = io_A; // @
assign FullAdder_5_io_b = io_B; // @
assign FullAdder_5_io_cin = FullAdder_4_io_cout; // @
assign FullAdder_6_io_a = io_A; // @
assign FullAdder_6_io_b = io_B; // @
assign FullAdder_6_io_cin = FullAdder_5_io_cout; // @
assign FullAdder_7_io_a = io_A; // @
assign FullAdder_7_io_b = io_B; // @
assign FullAdder_7_io_cin = FullAdder_6_io_cout; // @
endmodule

joe 发表于 2021-8-12 15:20:07

总结：
在val sum 和sum:=以及var sum和sum:=两种语法情况下，都可以正确产生verilog文件，用totalcommand工具对两种情况产生的verilgo文件进行内容比较，发现是一致的,
而且两种情况下产生的.fir文件的内容也是一样的。

查看完整版本: chisel中val/var,=和:=