xilinx DDR3 IP核使用代码
ug586中有相关介绍,但真的是麻烦,在IP核的example工程中有使用代码,但只适合example中使用,要想用于真正的项目还是移值量较大,黑金Mem_burst.v觉得不错,先帖出来,以后再分析和使用:/*本模块完成对ddr2 IP的包装,方便后续模块使用,也方便程序的移植,如果更换平台,更新这个文件即可*/
module mem_burst
#(
parameter MEM_DATA_BITS = 64,
parameter ADDR_BITS = 24
)
(
input rst, /*复位*/
input mem_clk, /*接口时钟*/
input rd_burst_req, /*读请求*/
input wr_burst_req, /*写请求*/
input rd_burst_len, /*读数据长度*/
input wr_burst_len, /*写数据长度*/
input rd_burst_addr, /*读首地址*/
input wr_burst_addr, /*写首地址*/
output rd_burst_data_valid, /*读出数据有效*/
output wr_burst_data_req, /*写数据信号*/
output rd_burst_data, /*读出的数据*/
input wr_burst_data, /*写入的数据*/
output rd_burst_finish, /*读完成*/
output wr_burst_finish, /*写完成*/
output burst_finish, /*读或写完成*/
///////////////////
output app_addr,
output app_cmd,
output app_en,
output app_wdf_data,
output app_wdf_end,
output app_wdf_mask,
output app_wdf_wren,
input app_rd_data,
input app_rd_data_end,
input app_rd_data_valid,
input app_rdy,
input app_wdf_rdy,
input ui_clk_sync_rst,
input init_calib_complete
);
assign app_wdf_mask = {MEM_DATA_BITS/8{1'b0}};
parameter IDLE = 3'd0;
parameter MEM_READ = 3'd1;
parameter MEM_READ_WAIT = 3'd2;
parameter MEM_WRITE= 3'd3;
parameter MEM_WRITE_WAIT = 3'd4;
parameter READ_END = 3'd5;
parameter WRITE_END = 3'd6;
parameter MEM_WRITE_FIRST_READ = 3'd7;
reg state;
reg rd_addr_cnt;
reg rd_data_cnt;
reg wr_addr_cnt;
reg wr_data_cnt;
reg app_cmd_r;
reg app_addr_r;
reg app_en_r;
reg app_wdf_end_r;
reg app_wdf_wren_r;
assign app_cmd = app_cmd_r;
assign app_addr = app_addr_r;
assign app_en = app_en_r;
assign app_wdf_end = app_wdf_end_r;
//assign wr_burst_data_req = wr_burst_data_req_r;
assign app_wdf_data = wr_burst_data;
assign app_wdf_wren = app_wdf_wren_r & app_wdf_rdy; //写DDR数据有效
assign rd_burst_finish = (state == READ_END);
assign wr_burst_finish = (state == WRITE_END);
assign burst_finish = rd_burst_finish | wr_burst_finish;
assign rd_burst_data = app_rd_data;
assign rd_burst_data_valid = app_rd_data_valid;
/* always@(posedge mem_clk or posedge rst)
begin
if(rst)
begin
app_wdf_wren_r <= 1'b0;
end
else
app_wdf_wren_r <= wr_burst_data_req_r; ``
end */
assign wr_burst_data_req = (state == MEM_WRITE) & app_wdf_rdy ; // 写ddr数据请求信号
always@(posedge mem_clk or posedge rst)
begin
if(rst)
begin
app_wdf_wren_r <= 1'b0;
end
else if(app_wdf_rdy)
app_wdf_wren_r <= wr_burst_data_req; //写DDR数据准备好
end
always@(posedge mem_clk or posedge rst)
begin
if(rst)
begin
state <= IDLE;
app_cmd_r <= 3'b000;
app_addr_r <= 0;
app_en_r <= 1'b0;
//wr_burst_data_req_r <= 1'b0;
rd_addr_cnt <= 0;
rd_data_cnt <= 0;
wr_addr_cnt <= 0;
wr_data_cnt <= 0;
app_wdf_end_r <= 1'b0;
//app_wdf_wren_r <= 1'b0;
end
else if(init_calib_complete ===1'b1)
begin
case(state)
IDLE:
begin
if(rd_burst_req)
begin
state <= MEM_READ;
app_cmd_r <= 3'b001; //读命令
app_addr_r <= {rd_burst_addr,3'd0}; //app的数据宽度256,ddr的数据宽度是32位,这里需要乘8,
app_en_r <= 1'b1; //命令有效
end
else if(wr_burst_req)
begin
state <= MEM_WRITE;
app_cmd_r <= 3'b000; //写命令
app_addr_r <= {wr_burst_addr,3'd0};
app_en_r <= 1'b1; //命令有效
wr_addr_cnt <= 0;
app_wdf_end_r <= 1'b1;
wr_data_cnt <= 0;
end
end
MEM_READ:
begin
if(app_rdy) //ddr用户接口空闲
begin
app_addr_r <= app_addr_r + 8; //app的数据宽度256,ddr的数据宽度是32位, 地址需要加8
if(rd_addr_cnt == rd_burst_len - 1) //发送了rd_burst_len的地址
begin
state <= MEM_READ_WAIT; //转到MEM_READ_WAIT状态接收数据
rd_addr_cnt <= 0;
app_en_r <= 1'b0; //命令无效
end
else
rd_addr_cnt <= rd_addr_cnt + 1;
end
if(app_rd_data_valid) //ddr3读取的数据有效
begin
if(rd_data_cnt == rd_burst_len - 1)//读取rd_burst_len长度的数据
begin
rd_data_cnt <= 0;
state <= READ_END; //读完成
end
else
begin
rd_data_cnt <= rd_data_cnt + 1; //读数据变量增加
end
end
end
MEM_READ_WAIT:
begin
if(app_rd_data_valid) //ddr3读取的数据有效
begin
if(rd_data_cnt == rd_burst_len - 1) //读取rd_burst_len长度的数据
begin
rd_data_cnt <= 0;
state <= READ_END; //读完成
end
else
begin
rd_data_cnt <= rd_data_cnt + 1; //读数据变量增加
end
end
end
MEM_WRITE:
begin
if(app_rdy) //ddr用户接口空闲
begin
app_addr_r <= app_addr_r + 8; //app的数据宽度256,ddr的数据宽度是32位, 地址需要加8
if(wr_addr_cnt == wr_burst_len - 1) //判断是否发送了wr_burst_len的地址的写命令
begin
app_wdf_end_r <= 1'b0;
app_en_r <= 1'b0; //命令无效
end
else
begin
wr_addr_cnt <= wr_addr_cnt + 1;
end
end
if(wr_burst_data_req) //写入ddr数据统计
begin
if(wr_data_cnt == wr_burst_len - 1) //等待buart长度的数据写入到DDR IP的FIFO里
begin
state <= MEM_WRITE_WAIT;
end
else
begin
wr_data_cnt <= wr_data_cnt + 1;
end
end
end
READ_END:
state <= IDLE;
MEM_WRITE_WAIT:
begin
if(app_rdy)
begin
app_addr_r <= app_addr_r + 8;
if(wr_addr_cnt == wr_burst_len - 1) //判断是否发送了wr_burst_len的地址的写命令
begin
app_wdf_end_r <= 1'b0;
app_en_r <= 1'b0;
if(app_wdf_rdy) //DDR数据已经写入完成
state <= WRITE_END;
end
else
begin
wr_addr_cnt <= wr_addr_cnt + 1;
end
end
else if(~app_en_r & app_wdf_rdy) //写DDR命令已经完成,并且DDR数据已经写入完成
state <= WRITE_END;
end
WRITE_END:
state <= IDLE;
default:
state <= IDLE;
endcase
end
end
endmodule
module ddr3
#(
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter CK_WIDTH = 1,
// # of CK/CK# outputs to memory.
parameter nCS_PER_RANK = 1,
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1,
// # of CKE outputs to memory.
parameter DM_WIDTH = 4,
// # of DM (data mask)
parameter ODT_WIDTH = 1,
// # of ODT outputs to memory.
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter DQ_WIDTH = 32,
// # of DQ (data)
parameter DQS_WIDTH = 4,
parameter DQS_CNT_WIDTH = 2,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 15,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 29,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 5250,
// Input Clock Period
parameter CLKFBOUT_MULT = 7,
// write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1,
// write PLL VCO divisor
parameter CLKOUT0_PHASE = 337.5,
// Phase for PLL output clock (CLKOUT0)
parameter CLKOUT0_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT0)
parameter CLKOUT1_DIVIDE = 2,
// VCO output divisor for PLL output clock (CLKOUT1)
parameter CLKOUT2_DIVIDE = 32,
// VCO output divisor for PLL output clock (CLKOUT2)
parameter CLKOUT3_DIVIDE = 8,
// VCO output divisor for PLL output clock (CLKOUT3)
parameter MMCM_VCO = 666,
// Max Freq (MHz) of MMCM VCO
parameter MMCM_MULT_F = 4,
// write MMCM VCO multiplier
parameter MMCM_DIVCLK_DIVIDE = 1,
// write MMCM VCO divisor
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100,
parameter DRAM_TYPE = "DDR3",
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter nCK_PER_CLK = 4,
// # of memory CKs per fabric CLK
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF",
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout ddr3_dq,
inout ddr3_dqs_n,
inout ddr3_dqs_p,
// Outputs
output ddr3_addr,
output ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_reset_n,
output ddr3_ck_p,
output ddr3_ck_n,
output ddr3_cke,
output ddr3_cs_n,
output ddr3_dm,
output ddr3_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
output tg_compare_error,
output init_calib_complete,
output ui_clk,
output ui_clk_sync_rst,
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
function integer STR_TO_INT;
input in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam DATA_WIDTH = 32;
localparam RANK_WIDTH = clogb2(RANKS);
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
//***************************************************************************
// Traffic Gen related parameters (derived)
//***************************************************************************
localparamTG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
localparam MASK_SIZE = DATA_WIDTH/8;
// Wire declarations
wire [(2*nCK_PER_CLK)-1:0] app_ecc_multiple_err;
wire [(2*nCK_PER_CLK)-1:0] app_ecc_single_err;
wire app_addr;
wire app_cmd;
wire app_en;
wire app_rdy;
wire app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_wdf_data;
wire app_wdf_end;
wire app_wdf_mask;
wire app_wdf_rdy;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire app_wdf_wren;
wire [(64+(2*APP_DATA_WIDTH))-1:0] error_status;
wire [(PAYLOAD_WIDTH/8)-1:0] cumlative_dq_lane_error;
wire mem_pattern_init_done;
wire tg_wr_data_counts;
wire tg_rd_data_counts;
wire modify_enable_sel;
wire data_mode_manual_sel;
wire addr_mode_manual_sel;
wire cmp_data;
reg cmp_data_r;
wire cmp_data_valid;
reg cmp_data_valid_r;
wire cmp_error;
wire [(PAYLOAD_WIDTH/8)-1:0] dq_error_bytelane_cmp;
wire clk;
wire rst;
wire dbg_sel_pi_incdec;
wire dbg_pi_f_inc;
wire dbg_pi_f_dec;
wire dbg_sel_po_incdec;
wire dbg_po_f_inc;
wire dbg_po_f_stg23_sel;
wire dbg_po_f_dec;
wire vio_modify_enable;
wire vio_data_mode_value;
wire vio_pause_traffic;
wire vio_addr_mode_value;
wire vio_instr_mode_value;
wire vio_bl_mode_value;
wire vio_fixed_bl_value;
wire vio_fixed_instr_value;
wire vio_data_mask_gen;
wire vio_tg_rst;
wire vio_dbg_sel_pi_incdec;
wire vio_dbg_pi_f_inc;
wire vio_dbg_pi_f_dec;
wire vio_dbg_sel_po_incdec;
wire vio_dbg_po_f_inc;
wire vio_dbg_po_f_stg23_sel;
wire vio_dbg_po_f_dec;
wire device_temp;
`ifdef SKIP_CALIB
// skip calibration wires
wire calib_tap_req;
reg calib_tap_load;
reg calib_tap_addr;
reg calib_tap_val;
reg calib_tap_load_done;
`endif
//***************************************************************************
assign ui_clk = clk;
assign ui_clk_sync_rst = rst;
// Start of User Design top instance
//***************************************************************************
// The User design is instantiated below. The memory interface ports are
// connected to the top-level and the application interface ports are
// connected to the traffic generator module. This provides a reference
// for connecting the memory controller to system.
//***************************************************************************
mig_7series_0 u_mig_7series_0
(
// Memory interface ports
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_we_n (ddr3_we_n),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_reset_n (ddr3_reset_n),
.init_calib_complete (init_calib_complete),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_odt (ddr3_odt),
// Application interface ports
.app_addr (app_addr),
.app_cmd (app_cmd),
.app_en (app_en),
.app_wdf_data (app_wdf_data),
.app_wdf_end (app_wdf_end),
.app_wdf_wren (app_wdf_wren),
.app_rd_data (app_rd_data),
.app_rd_data_end (app_rd_data_end),
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (clk),
.ui_clk_sync_rst (rst),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.device_temp (device_temp),
`ifdef SKIP_CALIB
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
`endif
.sys_rst (sys_rst)
);
// End of User Design top instance
wire wr_burst_data_req;
wire wr_burst_finish;
wire rd_burst_finish;
wire rd_burst_req;
wire wr_burst_req;
wire rd_burst_len;
wire wr_burst_len;
wire rd_burst_addr;
wire wr_burst_addr;
wire rd_burst_data_valid;
wire rd_burst_data;
wire wr_burst_data;
mem_burst
#(
.MEM_DATA_BITS(APP_DATA_WIDTH),
.ADDR_BITS(ADDR_WIDTH)
)
mem_burst_m0
(
.rst(rst), /*复位*/
.mem_clk(clk), /*接口时钟*/
.rd_burst_req(rd_burst_req), /*读请求*/
.wr_burst_req(wr_burst_req), /*写请求*/
.rd_burst_len(rd_burst_len), /*读数据长度*/
.wr_burst_len(wr_burst_len), /*写数据长度*/
.rd_burst_addr(rd_burst_addr), /*读首地址*/
.wr_burst_addr(wr_burst_addr), /*写首地址*/
.rd_burst_data_valid(rd_burst_data_valid), /*读出数据有效*/
.wr_burst_data_req(wr_burst_data_req), /*写数据信号*/
.rd_burst_data(rd_burst_data), /*读出的数据*/
.wr_burst_data(wr_burst_data), /*写入的数据*/
.rd_burst_finish(rd_burst_finish), /*读完成*/
.wr_burst_finish(wr_burst_finish), /*写完成*/
.burst_finish(), /*读或写完成*/
///////////////////
.app_addr(app_addr),
.app_cmd(app_cmd),
.app_en(app_en),
.app_wdf_data(app_wdf_data),
.app_wdf_end(app_wdf_end),
.app_wdf_mask(app_wdf_mask),
.app_wdf_wren(app_wdf_wren),
.app_rd_data(app_rd_data),
.app_rd_data_end(app_rd_data_end),
.app_rd_data_valid(app_rd_data_valid),
.app_rdy(app_rdy),
.app_wdf_rdy(app_wdf_rdy),
.ui_clk_sync_rst(),
.init_calib_complete(init_calib_complete)
);
wire error;
mem_test
#(
.MEM_DATA_BITS(APP_DATA_WIDTH),
.ADDR_BITS(ADDR_WIDTH)
)
mem_test_m0
(
.rst(rst), /*复位*/
.mem_clk(clk), /*接口时钟*/
.rd_burst_req(rd_burst_req), /*读请求*/
.wr_burst_req(wr_burst_req), /*写请求*/
.rd_burst_len(rd_burst_len), /*读数据长度*/
.wr_burst_len(wr_burst_len), /*写数据长度*/
.rd_burst_addr(rd_burst_addr), /*读首地址*/
.wr_burst_addr(wr_burst_addr), /*写首地址*/
.rd_burst_data_valid(rd_burst_data_valid), /*读出数据有效*/
.wr_burst_data_req(wr_burst_data_req), /*写数据信号*/
.rd_burst_data(rd_burst_data), /*读出的数据*/
.wr_burst_data(wr_burst_data), /*写入的数据*/
.rd_burst_finish(rd_burst_finish), /*读完成*/
.wr_burst_finish(wr_burst_finish), /*写完成*/
.error(error)
);
wire probe0;
wire probe1;
wire probe2;
wire probe3;
wire probe4;
wire probe5;
wire probe6;
wire probe7;
wire probe8;
wire probe9;
wire probe10;
ila_0 u_ila_0(
.clk(clk),
.probe0(probe0),
.probe1(probe1),
.probe2(probe2),
.probe3(probe3),
.probe4(probe4),
.probe5(probe5),
.probe6(probe6),
.probe7(probe7),
.probe8(probe8),
.probe9(probe9),
.probe10(probe10)
);
assign probe0 = rd_burst_req;
assign probe1 = wr_burst_req;
assign probe2 = rd_burst_data_valid;
assign probe3 = wr_burst_data_req;
assign probe4 = rd_burst_finish;
assign probe5 = wr_burst_finish;
assign probe6 = error;
assign probe7 = init_calib_complete;
assign probe8 = wr_burst_data;
assign probe9 = rd_burst_data;
assign probe10 = app_addr;
endmodule module top(
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_addr,
ddr3_ba,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_ck_p,
ddr3_ck_n,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_odt,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
clk_in1_0,
// migsysrefclk,
reset_0
// sys_rst,
// ui_clk,
// ui_clk_sync_rst
);
// Inouts
inout ddr3_dq;
inout ddr3_dqs_n;
inout ddr3_dqs_p;
// Outputs
output ddr3_addr;
output ddr3_ba;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
output ddr3_ck_p;
output ddr3_ck_n;
output ddr3_cke;
output ddr3_cs_n;
output ddr3_dm;
output ddr3_odt;
inout DDR_addr;
inout DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout DDR_dm;
inout DDR_dq;
inout DDR_dqs_n;
inout DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input clk_in1_0;
//output migsysrefclk;
input reset_0;
//output sys_rst;
//input ui_clk;
//input ui_clk_sync_rst;
wire DDR_addr;
wire DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire DDR_dm;
wire DDR_dq;
wire DDR_dqs_n;
wire DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire clk_in1_0;
wire migsysrefclk;
wire reset_0;
wire sys_rst;
wire ui_clk;
wire ui_clk_sync_rst;
ddr3 ddr3inst
(
// Memory interface ports
.ddr3_dq (ddr3_dq ),
.ddr3_dqs_n (ddr3_dqs_n ),
.ddr3_dqs_p (ddr3_dqs_p ),
.ddr3_addr (ddr3_addr ),
.ddr3_ba (ddr3_ba ),
.ddr3_ras_n (ddr3_ras_n ),
.ddr3_cas_n (ddr3_cas_n ),
.ddr3_we_n (ddr3_we_n ),
.ddr3_reset_n (ddr3_reset_n ),
.ddr3_ck_p (ddr3_ck_p ),
.ddr3_ck_n (ddr3_ck_n ),
.ddr3_cke (ddr3_cke ),
.ddr3_cs_n (ddr3_cs_n ),
.ddr3_dm (ddr3_dm ),
.ddr3_odt (ddr3_odt ),
.sys_clk_i (migsysrefclk),
.clk_ref_i (migsysrefclk),
.tg_compare_error(),
.init_calib_complete(),
.ui_clk(ui_clk),
.ui_clk_sync_rst(ui_clk_sync_rst),
.sys_rst(sys_rst)
);
design_1_wrapper wrapper
(
.DDR_addr (DDR_addr ),
.DDR_ba (DDR_ba ),
.DDR_cas_n (DDR_cas_n ),
.DDR_ck_n (DDR_ck_n ),
.DDR_ck_p (DDR_ck_p ),
.DDR_cke (DDR_cke ),
.DDR_cs_n (DDR_cs_n ),
.DDR_dm (DDR_dm ),
.DDR_dq (DDR_dq ),
.DDR_dqs_n (DDR_dqs_n ),
.DDR_dqs_p (DDR_dqs_p ),
.DDR_odt (DDR_odt ),
.DDR_ras_n (DDR_ras_n ),
.DDR_reset_n (DDR_reset_n ),
.DDR_we_n (DDR_we_n ),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn ),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp ),
.FIXED_IO_mio (FIXED_IO_mio ),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk ),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb ),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.clk_in1_0 (clk_in1_0 ),
.migsysrefclk (migsysrefclk ),
.reset_0 (reset_0 ),
.sys_rst (sys_rst ),
.ui_clk (ui_clk ),
.ui_clk_sync_rst (ui_clk_sync_rst )
);
endmodule
注意时间,先要看第一幅图中的总时间示意。
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