verilog中数据交换(1)
//直接将两个输入交叉输出module change_2in_2out (
input clk,enable,reset,
input in1,in2,
output out1,out2 //一个时钟周期之后 out1=in2,out2=in1
};
reg tmp1;
reg tmp2;
always @(posedge clk) begin
if(reset) begin
tmp1 <= 1'b0;
tmp2 <= 1'b0;
end
else if(enable == 1'b1) begin //enable必须是一个周期的脉冲信号
tmp1 <= in1;
tmp2 <= in2;
end
end
assign out1 = tmp2;
assign out2 = tmp1;
endmodule
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