两个寄存器互相赋值问题
今天在看一个chisel代码时发现其中有二句是这样写的：when(xxx条件) {
x := y
y := x
}
想来想去，这二句产生的verilog代码应该就是伪代码如下：
always@(posedge clk) begin
if(xxx条件) begin
x <= y
y <= x
end
end
查看chisel代码最后生成的verilgo代码如下：
module RealGCD(
input clock,
input reset,
output io_in_ready,
input io_in_valid,
input io_in_bits_a,
input io_in_bits_b,
output io_out_valid,
output io_out_bits
);
reg x; // @
reg _RAND_0;
reg y; // @
reg _RAND_1;
regp; // @
reg _RAND_2;
wire_T = ~p; // @
wire_T_2 = io_in_valid & _T; // @
wire_GEN_2 = _T_2 | p; // @
wire_T_3 = x > y; // @
wire _T_5 = y - x; // @
wire_T_6 = y == 16'h0; // @
assign io_in_ready = ~p; // @
assign io_out_valid = _T_6 & p; // @
assign io_out_bits = x; // @
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
x = _RAND_0;
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
y = _RAND_1;
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
p = _RAND_2;
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
always @(posedge clock) begin
if (p) begin
if (_T_3) begin
x <= y;
end else if (_T_2) begin
x <= io_in_bits_a;
end
end else if (_T_2) begin
x <= io_in_bits_a;
end
if (p) begin
if (_T_3) begin
y <= x;
end else begin
y <= _T_5;
end
end else if (_T_2) begin
y <= io_in_bits_b;
end
if (reset) begin
p <= 1'h0;
end else if (io_out_valid) begin
p <= 1'h0;
end else begin
p <= _GEN_2;
end
end
endmodule
通过上面红色代码可以看到，verilog代码确实如初始所想。这二句最终的作用是什么呢？ 互相赋值相等？？？
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