chisel双端口缓冲区
import chisel3._/**
* 双端口 256字节长度 8bit位宽的内存缓冲区
*/
class Memo extends Module{
val io = IO(new Bundle {
val wen = Input(Bool())
val wrAddr = Input(UInt(8.W))
val wrData = Input(UInt(8.W))
val ren = Input(Bool())
val rdAddr = Input(UInt(8.W))
val rdData = Output(UInt(8.W))
})
val mem = Mem(256,UInt(8.W)) //256数量，UInt(8.W) chisel类型数据
//写
when(io.wen) {
mem(io.wrAddr) := io.wrData
}
//读
io.rdData := 0.U //输出必须要有一个默认值
when(io.ren) {
io.rdData := mem(io.rdAddr)
}
}
生成的verilog代码如下：
module DBram(
input clock,
input reset,
input io_wen,
input io_wrAddr,
input io_wrData,
input io_ren,
input io_rdAddr,
output io_rdData
);
reg mem ; // @
reg _RAND_0;
wire mem__T_1_data; // @
wire mem__T_1_addr; // @
wire mem__T_data; // @
wire mem__T_addr; // @
wiremem__T_mask; // @
wiremem__T_en; // @
assign mem__T_1_addr = io_rdAddr;
assign mem__T_1_data = mem; // @
assign mem__T_data = io_wrData;
assign mem__T_addr = io_wrAddr;
assign mem__T_mask = 1'h1;
assign mem__T_en = io_wen;
assign io_rdData = io_ren ? mem__T_1_data : 8'h0; // @
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 256; initvar = initvar+1)
mem = _RAND_0;
`endif // RANDOMIZE_MEM_INIT
`endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
always @(posedge clock) begin
if(mem__T_en & mem__T_mask) begin
mem <= mem__T_data; // @
end
end
endmodule
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