手把手教你开始搭建Risc-v Rocket环境(9)
29：joe@joe-Inspiron-7460:~/rocketchip/rocket-chip/emulator$ cd ../vsimjoe@joe-Inspiron-7460:~/rocketchip/rocket-chip/vsim$ makemkdir -p /home/joe/rocketchip/rocket-chip/vsim/generated-src/cd /home/joe/rocketchip/rocket-chip && java -Xmx2G -Xss8M -XX:MaxPermSize=256M -jar /home/joe/rocketchip/rocket-chip/sbt-launch.jar "runMain freechips.rocketchip.system.Generator /home/joe/rocketchip/rocket-chip/vsim/generated-src freechips.rocketchip.system TestHarness freechips.rocketchip.system DefaultConfig"Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0 Loading settings from plugins.sbt ... Loading project definition from /home/joe/rocketchip/rocket-chip/project Loading settings from build.sbt ... Loading settings from build.sbt ... Loading settings from build.sbt ...Using addons: Set current project to rocketchip (in build file:/home/joe/rocketchip/rocket-chip/) Multiple main classes detected.Run 'show discoveredMainClasses' to see the list Running freechips.rocketchip.system.Generator /home/joe/rocketchip/rocket-chip/vsim/generated-src freechips.rocketchip.system TestHarness freechips.rocketchip.system DefaultConfig Elaborating design...Interrupt map (2 harts 2 interrupts): => dut
/dts-v1/;
/ { #address-cells = <1>; #size-cells = <1>; compatible = "freechips,rocketchip-unknown-dev"; model = "freechips,rocketchip-unknown"; L13: cpus { #address-cells = <1>; #size-cells = <0>; L5: cpu@0 { clock-frequency = <0>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; d-cache-size = <16384>; d-tlb-sets = <1>; d-tlb-size = <32>; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <64>; i-cache-size = <16384>; i-tlb-sets = <1>; i-tlb-size = <32>; mmu-type = "riscv,sv39"; next-level-cache = <&L7>; reg = <0>; riscv,isa = "rv64imafdc"; status = "okay"; timebase-frequency = <1000000>; tlb-split; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; }; L7: memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; }; L12: soc { #address-cells = <1>; #size-cells = <1>; compatible = "freechips,rocketchip-unknown-soc", "simple-bus"; ranges; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; reg = <0x2000000 0x10000>; reg-names = "control"; }; L2: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; interrupts-extended = <&L3 65535>; reg = <0x0 0x1000>; reg-names = "control"; }; L10: error-device@3000 { compatible = "sifive,error0"; reg = <0x3000 0x1000>; reg-names = "mem"; }; L6: external-interrupts { interrupt-parent = <&L0>; interrupts = <1 2>; }; L0: interrupt-controller@c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; interrupt-controller; interrupts-extended = <&L3 11 &L3 9>; reg = <0xc000000 0x4000000>; reg-names = "control"; riscv,max-priority = <3>; riscv,ndev = <2>; }; L8: mmio-port-axi4@60000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges = <0x60000000 0x60000000 0x20000000>; }; L9: rom@10000 { compatible = "sifive,rom0"; reg = <0x10000 0x10000>; reg-names = "mem"; }; };};
Generated Address Map 0 - 1000 ARWXdebug-controller@0 3000 - 4000 ARWXerror-device@3000 10000 - 20000R XC rom@10000 2000000 -2010000 ARW clint@2000000 c000000 - 10000000 ARW interrupt-controller@c000000 60000000 - 80000000RWXmmio-port-axi4@60000000 80000000 - 90000000RWXC memory@80000000
Done elaborating. Total time: 20 s, completed 2018-6-23 22:11:22mkdir -p /home/joe/rocketchip/rocket-chip/vsim/generated-src/java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp "/home/joe/rocketchip/rocket-chip/firrtl/utils/bin/firrtl.jar":""/home/joe/rocketchip/rocket-chip/target/scala-2.11/classes:/home/joe/rocketchip/rocket-chip/chisel3/target/scala-2.11/*"" firrtl.Driver -i /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.fir -o /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.v -X verilog --infer-rw TestHarness --repl-seq-mem -c:TestHarness:-o:/home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.conf -faf /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.anno.json -td /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig/Java HotSpot(TM) 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0Total FIRRTL Compile Time: 52809.2 mscd /home/joe/rocketchip/rocket-chip/vsim/generated-src && \rm -f /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v && \/home/joe/rocketchip/rocket-chip/scripts/vlsi_mem_gen /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.conf >> /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp && \mv /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v.tmp /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.vcd . && \rm -rf csrc && \vcs -full64 -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet +rad +v2k +vcs+lic+wait +vc+list -CC "-I/include" -CC "-I/home/joe/rocketchip/rocket-chip/riscv-tools/riscv-gnu-toolchain/include" -CC "-std=c++11" -CC "-Wl,-rpath,/home/joe/rocketchip/rocket-chip/riscv-tools/riscv-gnu-toolchain/lib" /home/joe/rocketchip/rocket-chip/riscv-tools/riscv-gnu-toolchain/lib/libfesvr.so -sverilog +incdir+/home/joe/rocketchip/rocket-chip/vsim/generated-src +define+CLOCK_PERIOD=1.0 /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.v /home/joe/rocketchip/rocket-chip/vsim/generated-src/freechips.rocketchip.system.DefaultConfig.behav_srams.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/TestDriver.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/SimDTM.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/SimJTAG.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/plusarg_reader.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/ClockDivider2.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/ClockDivider3.v /home/joe/rocketchip/rocket-chip/src/main/resources/vsrc/AsyncResetReg.v/home/joe/rocketchip/rocket-chip/src/main/resources/csrc/SimDTM.cc /home/joe/rocketchip/rocket-chip/src/main/resources/csrc/SimJTAG.cc /home/joe/rocketchip/rocket-chip/src/main/resources/csrc/remote_bitbang.cc +define+PRINTF_COND=TestDriver.printf_cond +define+STOP_COND=!TestDriver.reset +define+RANDOMIZE_MEM_INIT +define+RANDOMIZE_REG_INIT +define+RANDOMIZE_GARBAGE_ASSIGN +define+RANDOMIZE_INVALID_ASSIGN +libext+.v-o ./simv-freechips.rocketchip.system-DefaultConfig \-debug_pp \
/bin/bash: 行 2: vcs: 未找到命令Makefrag:66: recipe for target 'simv-freechips.rocketchip.system-DefaultConfig' failedmake: *** Error 127通过后面几行的错误提示，说明没有安装SYNOPSYS公司的VCS。这不是本系列帖子的主题方面的内容了。手把手教你开始搭建Risc-v Rocket环境 全部结束。 喜欢risc-v，不错，:victory:
页:
[1]