chisel实现Moore状态机
有限状态机(FSM finite-state machine)是数字电路中的基本模块,一个FSM可以被描述为一些状态states和条件.一个FSM有一个初始状态,就是在RESET时被确定的状态。FSMs也被称为同步时序电路。
FSM的实现包括三个部分:
1)一个具有现在状态的寄存器
2)组合逻辑 它根据现在状态和输入计算下个状态
3)组合逻辑能够计算FSM的输出
当输出只取决于当前状态时称为Moore状态机,当输出不仅取决于当前状态,还同时取决于当前输入称为Mealy状态机.
下图是一个简单的FSM图:
根据上图写对应的chisel代码如下:
import chisel3._
import chisel3.util._
class SimpleFSM extends Module{
val io = IO(new Bundle {
val badEvent = Input(Bool())
val clear = Input(Bool())
val ringBell = Output(Bool())
})
//状态
val green :: orange :: red ::Nil = Enum(3)//chisel3.util.Enum(n:Int)产生[0,n)每个值(UInt)都是唯一的seq
//状态寄存器
val stateReg = RegInit(green) //用chisel类型初始化RegInit寄存器
//下个状态逻辑判断
switch(stateReg) {
is (green) {
when (io.badEvent) {
stateReg := orange
}
}
is (orange) {
when (io.badEvent) {
stateReg := red
} .elsewhen(io.clear) {
stateReg := green
}
}
is (red) {
when (io.clear) {
stateReg := green
}
}
}
//输出组合逻辑
io.ringBell := stateReg === red
}
注意:我们并没有引入next_state作为寄存器输入。
计数器、状态机、FIFO是常用三大基础,都需要用chisel实现它们。 生成的verilog文件内容如下:
module SimpleFSM(
input clock,
input reset,
input io_badEvent,
input io_clear,
outputio_ringBell
);
reg stateReg; // @
reg _RAND_0;
wire_T = 2'h0 == stateReg; // @
wire_T_1 = 2'h1 == stateReg; // @
wire_T_2 = 2'h2 == stateReg; // @
assign io_ringBell = stateReg == 2'h2; // @
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
stateReg = _RAND_0;
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end // initial
`endif // SYNTHESIS
always @(posedge clock) begin
if (reset) begin
stateReg <= 2'h0;
end else if (_T) begin
if (io_badEvent) begin
stateReg <= 2'h1;
end
end else if (_T_1) begin
if (io_badEvent) begin
stateReg <= 2'h2;
end else if (io_clear) begin
stateReg <= 2'h0;
end
end else if (_T_2) begin
if (io_clear) begin
stateReg <= 2'h0;
end
end
end
endmodule
简化形式如下:
module SimpleFSM(
input clock,
input reset,
input io_badEvent,
input io_clear,
outputio_ringBell
);
reg stateReg; // @
reg _RAND_0;
wire_T = 2'h0 == stateReg; // @
wire_T_1 = 2'h1 == stateReg; // @
wire_T_2 = 2'h2 == stateReg; // @
assign io_ringBell = stateReg == 2'h2; // @
always @(posedge clock) begin
if (reset) begin
stateReg <= 2'h0;
end else if (_T) begin
if (io_badEvent) begin
stateReg <= 2'h1;
end
end else if (_T_1) begin
if (io_badEvent) begin
stateReg <= 2'h2;
end else if (io_clear) begin
stateReg <= 2'h0;
end
end else if (_T_2) begin
if (io_clear) begin
stateReg <= 2'h0;
end
end
end
endmodule
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